Fix lint_off/lint_on pairs on same line as warning

Changes

@@ -49,6 +49,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Fix Verilator core dump on wide integer divides, bug178. [Byron Bradley]
 
+**** Fix lint_off/lint_on meta comments on same line as warning.
+
 * Verilator 3.720 2009/10/26
 
 **   Support little endian bit vectors ("reg [0:2] x;").

src/V3Error.cpp

@@ -122,11 +122,12 @@ void FileLine::warnLintOff(bool flag) {
 }
 
 FileLine* FileLine::copyOrSameFileLine() {
+    // When a fileline is "used" to produce a node, calls this function.
     // Return this, or a copy of this
     // There are often more than one token per line, thus we use the
-    // same pointer as long as we're on the same line.
+    // same pointer as long as we're on the same line, file & warn state.
     static FileLine* lastNewp = NULL;
-    if (lastNewp && *lastNewp == *this) {
+    if (lastNewp && *lastNewp == *this) {  // Compares lineno, filename, etc
 	return lastNewp;
     }
     FileLine* newp = new FileLine(this);

src/V3Error.h

@@ -270,8 +270,9 @@ public:
 
     // METHODS
     void	v3errorEnd(ostringstream& str);
-    inline bool operator==(FileLine rhs) { return (m_lineno==rhs.m_lineno && m_filename==rhs.m_filename); }
-
+    inline bool operator==(FileLine rhs) {
+	return (m_lineno==rhs.m_lineno && m_filename==rhs.m_filename && m_warnOn==rhs.m_warnOn);
+    }
     static void deleteAllRemaining();
 };
 ostream& operator<<(ostream& os, FileLine* fileline);

test_regress/t/t_flag_future.pl

@@ -8,11 +8,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 
 compile (
-	 verilator_flags2 => [qw(-Wfuture-FUTURE1 -Wfuture-FUTURE2)],
-	 );
-
-execute (
-	 check_finished=>1,
+	 verilator_flags2 => [qw(--lint-only -Wfuture-FUTURE1 -Wfuture-FUTURE2)],
 	 );
 
 ok(1);

test_regress/t/t_metacmt_onoff.pl

@@ -0,0 +1,24 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 verilator_flags2 => [qw(--lint-only)],
+	 verilator_make_gcc => 0,
+	 make_top_shell => 0,
+	 make_main => 0,
+	 fails=>$Self->{vlt},
+	 expect=>
+'%Warning-LITENDIAN: t/t_metacmt_onoff.v:\d+: Little bit endian vector: MSB < LSB of bit range: 0:1
+%Warning-LITENDIAN: Use "/\* verilator lint_off LITENDIAN \*/" and lint_on around source to disable this message.
+%Warning-LITENDIAN: t/t_metacmt_onoff.v:\d+: Little bit endian vector: MSB < LSB of bit range: 0:3
+%Error: Exiting due to.*',
+	 );
+
+ok(1);
+1;

test_regress/t/t_metacmt_onoff.v

@@ -0,0 +1,10 @@
+// DESCRIPTION: Verilator: Verilog Test module
+
+module t;
+   // Test turning on and off a message on the same line; only middle reg shouldn't warn
+   reg [0:1] show1; /*verilator lint_off LITENDIAN*/ reg [0:2] ign2; /*verilator lint_on LITENDIAN*/  reg [0:3] show3;
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule