Fix signed/unsigned parameter types (#3866)

docs/CONTRIBUTORS

@@ -52,6 +52,7 @@ Jake Merdich
 James Hanlon
 James Hutchinson
 James Pallister
+James Shi
 Jamey Hicks
 Jamie Iles
 Jan Van Winkel

src/V3Param.cpp

@@ -330,6 +330,9 @@ class ParamProcessor final {
             key += " ";
             key += paramValueKey(dtypep->subDTypep());
         } else if (const AstBasicDType* const dtypep = VN_CAST(nodep, BasicDType)) {
+            if (dtypep->isSigned()) {
+                key += " signed";
+            }
             if (dtypep->isRanged()) {
                 key += "[" + cvtToStr(dtypep->left()) + ":" + cvtToStr(dtypep->right()) + "]";
             }

test_regress/t/t_param_type_cmp.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_param_type_cmp.v

@@ -0,0 +1,48 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2004 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t ();
+
+   logic [2:0] a;
+   logic [2:0] b;
+
+   logic signed_out;
+   logic unsigned_out;
+
+   cmp #(.element_type(logic signed [2:0])) signed_cmp (.a(a), .b(b), .c(signed_out));
+   cmp #(.element_type(logic [2:0])) unsigned_cmp (.a(a), .b(b), .c(unsigned_out));
+
+   initial a = 3'b001;
+   initial b = 3'b111;
+
+   initial begin
+      if (signed_out !== 1'b0) begin
+         $display("%%Error: bad signed comparison %b < %b: got=%d exp=%d", a, b, signed_out, 1'b0);
+         $stop;
+      end
+      if (unsigned_out !== 1'b1) begin
+         $display("%%Error: bad unsigned comparison %b < %b: got=%d exp=%d", a, b, unsigned_out, 1'b1);
+         $stop;
+      end
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule
+
+module cmp
+#(
+    parameter type element_type = logic
+)
+(
+   input element_type a,
+   input element_type b,
+   output logic c
+);
+
+   assign c = a < b;
+
+endmodule