Add support for package imports preceeding parameters in interfaces (#2714)

Co-authored-by: James Hanlon <mail@jameswhanlon.com>

src/verilog.y

@@ -1403,7 +1403,7 @@ portSig<nodep>:
 
 interface_declaration:		// IEEE: interface_declaration + interface_nonansi_header + interface_ansi_header:
 	//			// timeunits_delcarationE is instead in interface_item
-		intFront parameter_port_listE portsStarE ';'
+		intFront importsAndParametersE portsStarE ';'
 			interface_itemListE yENDINTERFACE endLabelE
 			{ if ($2) $1->addStmtp($2);
 			  if ($3) $1->addStmtp($3);

test_regress/t/t_interface_import_param.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_interface_import_param.v

@@ -0,0 +1,47 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// A test that a package import declaration can preceed a parameter port list
+// in an interface declaration. See 25.3 of the 1800-2017 LRM.
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2013 by Jeremy Bennett.
+// SPDX-License-Identifier: CC0-1.0
+
+package bus_pkg;
+  parameter WIDTH = 8;
+endpackage
+
+interface simple_bus
+  import bus_pkg::*; // Import preceding parameters.
+  #(p_width = WIDTH)
+   (input logic clk);
+
+   logic req, gnt;
+   logic [p_width-1:0] addr;
+   logic [p_width-1:0] data;
+
+   modport slave(input req, addr, clk,
+                 output gnt,
+                 input  data);
+
+   modport master(input gnt, clk,
+                  output req, addr,
+                  output data);
+
+endinterface
+
+module mem(simple_bus a);
+   logic avail;
+   always @(posedge a.clk)
+     a.gnt <= a.req & avail;
+   initial begin
+      if ($bits(a.data) != 8) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule
+
+module t (input clk);
+   simple_bus sb(clk);
+   mem mem(sb.slave);
+endmodule