Tests: Parameter bug case

src/V3Param.cpp

@@ -159,6 +159,7 @@ private:
 	nodep->deleteTree(); nodep=NULL;
     }
     virtual void visit(AstGenIf* nodep, AstNUser*) {
+	UINFO(9,"  GENIF "<<nodep<<endl);
 	nodep->condp()->iterateAndNext(*this);
 	V3Width::widthParamsEdit(nodep);  // Param typed widthing will NOT recurse the body
 	V3Const::constifyParamsEdit(nodep->condp());  // condp may change
@@ -181,11 +182,13 @@ private:
     virtual void visit(AstGenFor* nodep, AstNUser*) {
 	// We parse a very limited form of FOR, so we don't need to do a full
 	// simulation to unroll the loop
+	UINFO(9,"  GENFOR "<<nodep<<endl);
 	V3Width::widthParamsEdit(nodep);  // Param typed widthing will NOT recurse the body
 	// Note V3Unroll will replace some AstVarRef's to the loop variable with constants
 	V3Unroll::unrollGen(nodep); nodep=NULL;
     }
     virtual void visit(AstGenCase* nodep, AstNUser*) {
+	UINFO(9,"  GENCASE "<<nodep<<endl);
 	AstNode* keepp = NULL;
 	nodep->exprp()->iterateAndNext(*this);
 	V3Case::caseLint(nodep);

test_regress/t/t_genvar_misuse_bad.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} and $Self->skip("Verilator unsupported, bug408");
+
+compile (
+	 v_flags2 => ["--lint-only"],
+	 fails=>1,
+	 expect=>
+'.*%Error: t/t_genvar_misuse_bad.v:\d+: Use of genvar where not convertible to constant: i
+%Error: Exiting due to.*',
+	 );
+
+ok(1);
+1;

test_regress/t/t_genvar_misuse_bad.v

@@ -0,0 +1,17 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Wilson Snyder.
+// See bug408
+
+module top
+  (
+   output logic [1:0] q,
+   input logic [1:0]  d,
+   input logic 	      clk
+   );
+
+   genvar 	     i;
+   assign 	     q[i] = d[i];
+endmodule
+