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Commentary: Changes update

This commit is contained in:
Wilson Snyder 2026-05-22 17:57:11 -04:00
parent c99aa8ede5
commit c0dc77c908
14 changed files with 716 additions and 455 deletions
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8
Changes
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@ -35,9 +35,12 @@ Verilator 5.049 devel
* Support property abort operators (accept_on, reject_on) (#7578). [Yilou Wang]
* Support procedural concurrent assertions with inferred clock (#7581). [Yilou Wang]
* Support calling interface functions without parens (#7584). [Krzysztof Bieganski, Antmicro Ltd.]
* Support streaming on queues (#7597). [Benjamin Collier, Secturion Systems, Inc.]
* Support FSM detection in primitive wrappers (#7607). [Yogish Sekhar]
* Support busses with mix of pullup/pulldown (#7632). [Lucas Amaral]
* Add peak memory usage to `--stats`. [Geza Lore, Testorrent USA, Inc.]
* Add error on mixed-initialization (#7352) (#7357).
* Improve `--coverage-fsm` (#7490) (#7529) (#7561) (#7573). [Yogish Sekhar]
* Improve `--coverage-fsm` (#7490) (#7529) (#7561) (#7573) (#7619). [Yogish Sekhar]
* Change `+verilator+seed` to default to 1, and 0 to randomly select (#7325) (#7516). [Miguel]
* Change JSON to include parameter constant mnemonics for FSM Coverage (#7531). [Yogish Sekhar]
* Optimize emitting to_string() for compiler speedup (#7468). [Jakub Michalski, Antmicro Ltd.]
@ -77,6 +80,9 @@ Verilator 5.049 devel
* Fix type parameters order (#7615). [Kamil Danecki, Antmicro Ltd.]
* Fix unique_index method on assoc arrays with values differing from the keys (#7616). [Pawel Klopotek]
* Fix wide equality comparison in unpacked structs (#7618). [Geza Lore, Testorrent USA, Inc.]
* Fix force determinism (#7620) (#7637). [Artur Bieniek, Antmicro Ltd.]
* Fix reference counting for modport task references (#7628). [Nick Brereton]
* Fix implicit conversions of VlWide (#7642). [Geza Lore, Testorrent USA, Inc.]
Verilator 5.048 2026-04-26

2
docs/spelling.txt
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@ -430,6 +430,7 @@ Sasselli
Sauter
Scharrer
Schless
Secturion
Seitz
Shahid
Shahrestani
@ -866,6 +867,7 @@ impot
incdir
includer
incrementing
inferable
inferfaces
informationals
inhibitSim

2
src/V3DfgSynthesize.cpp
View File

@ -1813,7 +1813,7 @@ class AstToDfgSynthesize final {
if (!resolvedp) continue;
// Add to map for next loop
const bool newEntry = resolvedDrivers.emplace(&var, resolvedp).second;
UASSERT_OBJ(newEntry, &var, "Dupliacte driver");
UASSERT_OBJ(newEntry, &var, "Duplicate driver");
}
// Revert and remove drivers of multi-driven variables
revert(m_ctx.m_synt.revertMultidrive);

2
src/V3Inline.cpp
View File

@ -642,7 +642,7 @@ void inlineCell(AstNodeModule* modp, AstCell* cellp, bool last) {
// Connect the pins on the instance
for (AstPin* pinp = cellp->pinsp(); pinp; pinp = VN_AS(pinp->nextp(), Pin)) {
if (!pinp->exprp()) continue;
UINFO(6, "Conecting port " << pinp->modVarp());
UINFO(6, "Connecting port " << pinp->modVarp());
UINFO(6, " of instance " << cellp);
// Make sure the conneccted pin expression is always a VarRef or a Const

178
test_regress/t/t_fsm_register_wrapper.out
View File

@ -110,13 +110,13 @@
end
my_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
);
endmodule
@ -152,13 +152,13 @@
end
my_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
);
endmodule
@ -194,13 +194,13 @@
end
prim_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.d_i(state_d),
.q_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.d_i(state_d),
.q_o(state_q)
);
endmodule
@ -236,13 +236,13 @@
end
prim_sparse_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
);
endmodule
@ -274,13 +274,13 @@
end
my_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
);
endmodule
@ -316,13 +316,13 @@
end
my_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
);
endmodule
@ -358,13 +358,13 @@
end
odd_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk(clk),
.rst_n(rst_n),
.din(state_d),
.dout(state_q)
.clk(clk),
.rst_n(rst_n),
.din(state_d),
.dout(state_q)
);
endmodule
@ -400,13 +400,13 @@
end
my_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d[1:0]),
.state_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d[1:0]),
.state_o(state_q)
);
endmodule
@ -434,11 +434,11 @@
end
ambiguous_fsm_flop u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.d_i(state_d),
.state_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.d_i(state_d),
.state_o(state_q)
);
endmodule
@ -474,13 +474,13 @@
end
odd_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk(clk),
.rst_n(rst_n),
.din(state_d),
.dout(state_q)
.clk(clk),
.rst_n(rst_n),
.din(state_d),
.dout(state_q)
);
endmodule
@ -508,15 +508,55 @@
end
end
fsm_auto auto_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_noargs_hint noargs_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_prim prim_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_sparse_prim sparse_prim_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_ifchain ifchain_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_wide_sparse wide_sparse_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_annotated annotated_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_non_simple non_simple_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_ambiguous ambiguous_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_ignored ignored_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_auto auto_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_noargs_hint noargs_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_prim prim_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_sparse_prim sparse_prim_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_ifchain ifchain_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_wide_sparse wide_sparse_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_annotated annotated_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_non_simple non_simple_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_ambiguous ambiguous_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_ignored ignored_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
endmodule

178
test_regress/t/t_fsm_register_wrapper.v
View File

@ -101,13 +101,13 @@ module fsm_auto (
end
my_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
);
endmodule
@ -135,13 +135,13 @@ module fsm_noargs_hint (
end
my_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
);
endmodule
@ -169,13 +169,13 @@ module fsm_prim (
end
prim_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.d_i(state_d),
.q_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.d_i(state_d),
.q_o(state_q)
);
endmodule
@ -203,13 +203,13 @@ module fsm_sparse_prim (
end
prim_sparse_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
);
endmodule
@ -241,13 +241,13 @@ module fsm_ifchain (
end
my_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
);
endmodule
@ -275,13 +275,13 @@ module fsm_wide_sparse (
end
my_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
);
endmodule
@ -309,13 +309,13 @@ module fsm_annotated (
end
odd_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk(clk),
.rst_n(rst_n),
.din(state_d),
.dout(state_q)
.clk(clk),
.rst_n(rst_n),
.din(state_d),
.dout(state_q)
);
endmodule
@ -343,13 +343,13 @@ module fsm_non_simple (
end
my_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d[1:0]),
.state_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d[1:0]),
.state_o(state_q)
);
endmodule
@ -377,11 +377,11 @@ module fsm_ambiguous (
end
ambiguous_fsm_flop u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.d_i(state_d),
.state_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.d_i(state_d),
.state_o(state_q)
);
endmodule
@ -409,13 +409,13 @@ module fsm_ignored (
end
odd_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk(clk),
.rst_n(rst_n),
.din(state_d),
.dout(state_q)
.clk(clk),
.rst_n(rst_n),
.din(state_d),
.dout(state_q)
);
endmodule
@ -443,14 +443,54 @@ module t (
end
end
fsm_auto auto_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_noargs_hint noargs_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_prim prim_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_sparse_prim sparse_prim_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_ifchain ifchain_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_wide_sparse wide_sparse_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_annotated annotated_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_non_simple non_simple_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_ambiguous ambiguous_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_ignored ignored_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_auto auto_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_noargs_hint noargs_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_prim prim_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_sparse_prim sparse_prim_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_ifchain ifchain_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_wide_sparse wide_sparse_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_annotated annotated_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_non_simple non_simple_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_ambiguous ambiguous_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_ignored ignored_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
endmodule

276
test_regress/t/t_fsm_register_wrapper_noinline.out
View File

@ -50,13 +50,13 @@
logic [Width-1:0] state_raw;
prim_flop #(
.Width(Width),
.ResetValue(ResetValue)
.Width(Width),
.ResetValue(ResetValue)
) u_state_flop (
.clk_i(clk_i),
.rst_ni(rst_ni),
.d_i(state_i),
.q_o(state_raw)
.clk_i(clk_i),
.rst_ni(rst_ni),
.d_i(state_i),
.q_o(state_raw)
);
assign state_o = StateEnumT'(state_raw);
@ -215,13 +215,13 @@
end
my_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
);
endmodule
@ -257,13 +257,13 @@
end
prim_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.d_i(state_d),
.q_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.d_i(state_d),
.q_o(state_q)
);
endmodule
@ -299,13 +299,13 @@
end
prim_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.d_i(state_d),
.q_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.d_i(state_d),
.q_o(state_q)
);
endmodule
@ -340,14 +340,14 @@
end
prim_sparse_fsm_flop #(
.StateEnumT(state_t),
.Width($bits(state_t)),
.ResetValue(S0)
.StateEnumT(state_t),
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
);
endmodule
@ -382,14 +382,14 @@
end
prim_sparse_fsm_flop #(
.StateEnumT(state_t),
.Width($bits(state_t)),
.ResetValue(S0)
.StateEnumT(state_t),
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
);
endmodule
@ -425,13 +425,13 @@
end
active_high_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk(clk),
.rst(rst),
.d(state_d),
.q(state_q)
.clk(clk),
.rst(rst),
.d(state_d),
.q(state_q)
);
endmodule
@ -467,13 +467,13 @@
end
active_high_rst_i_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk(clk),
.rst_i(rst),
.d(state_d),
.q(state_q)
.clk(clk),
.rst_i(rst),
.d(state_d),
.q(state_q)
);
endmodule
@ -507,11 +507,11 @@
end
no_reset_fsm_flop #(
.Width($bits(state_t))
.Width($bits(state_t))
) u_state_regs (
.clk(clk),
.d(state_d),
.q(state_q)
.clk(clk),
.d(state_d),
.q(state_q)
);
endmodule
@ -546,12 +546,12 @@
end
reset_no_param_fsm_flop #(
.Width($bits(state_t))
.Width($bits(state_t))
) u_state_regs (
.clk(clk),
.rst_n(rst_n),
.d(state_d),
.q(state_q)
.clk(clk),
.rst_n(rst_n),
.d(state_d),
.q(state_q)
);
endmodule
@ -586,13 +586,13 @@
end
sync_reset_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk(clk),
.my_reset(parent_reset),
.d(state_d),
.q(state_q)
.clk(clk),
.my_reset(parent_reset),
.d(state_d),
.q(state_q)
);
endmodule
@ -628,13 +628,13 @@
end
custom_reset_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk(clk),
.my_reset(parent_reset),
.d(state_d),
.q(state_q)
.clk(clk),
.my_reset(parent_reset),
.d(state_d),
.q(state_q)
);
endmodule
@ -670,13 +670,13 @@
end
custom_reset_active_high_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk(clk),
.my_reset(parent_reset),
.d(state_d),
.q(state_q)
.clk(clk),
.my_reset(parent_reset),
.d(state_d),
.q(state_q)
);
endmodule
@ -704,11 +704,11 @@
end
ambiguous_fsm_flop u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.d_i(state_d),
.state_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.d_i(state_d),
.state_o(state_q)
);
endmodule
@ -744,13 +744,13 @@
end
my_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
);
endmodule
@ -792,13 +792,13 @@
end
my_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
);
/* verilator lint_on BLKANDNBLK */
endmodule
@ -830,21 +830,79 @@
end
end
fsm_auto auto_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_prim prim_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_prim_override prim_override_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_sparse_prim sparse_prim_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_sparse_prim_override sparse_prim_override_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_active_high active_high_u (.clk(clk), .rst(rst), .start(start));
fsm_active_high_rst_i active_high_rst_i_u (.clk(clk), .rst(rst), .start(start));
fsm_no_reset no_reset_u (.clk(clk), .start(start));
fsm_reset_no_param reset_no_param_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_sync_reset_unknown_polarity sync_reset_u (.clk(clk), .parent_reset(rst), .start(start));
fsm_custom_reset_parent_polarity custom_reset_u (.clk(clk), .parent_reset(rst_n), .start(start));
fsm_auto auto_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_prim prim_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_prim_override prim_override_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_sparse_prim sparse_prim_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_sparse_prim_override sparse_prim_override_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_active_high active_high_u (
.clk(clk),
.rst(rst),
.start(start)
);
fsm_active_high_rst_i active_high_rst_i_u (
.clk(clk),
.rst(rst),
.start(start)
);
fsm_no_reset no_reset_u (
.clk(clk),
.start(start)
);
fsm_reset_no_param reset_no_param_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_sync_reset_unknown_polarity sync_reset_u (
.clk(clk),
.parent_reset(rst),
.start(start)
);
fsm_custom_reset_parent_polarity custom_reset_u (
.clk(clk),
.parent_reset(rst_n),
.start(start)
);
fsm_custom_reset_active_high custom_reset_active_high_u (
.clk(clk), .parent_reset(rst), .start(start));
fsm_ambiguous_ignored ambiguous_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_missing_reset_param missing_reset_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_competing_direct competing_u (.clk(clk), .rst_n(rst_n), .start(start));
.clk(clk),
.parent_reset(rst),
.start(start)
);
fsm_ambiguous_ignored ambiguous_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_missing_reset_param missing_reset_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_competing_direct competing_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
endmodule

276
test_regress/t/t_fsm_register_wrapper_noinline.v
View File

@ -49,13 +49,13 @@ module prim_sparse_fsm_flop #(
logic [Width-1:0] state_raw;
prim_flop #(
.Width(Width),
.ResetValue(ResetValue)
.Width(Width),
.ResetValue(ResetValue)
) u_state_flop (
.clk_i(clk_i),
.rst_ni(rst_ni),
.d_i(state_i),
.q_o(state_raw)
.clk_i(clk_i),
.rst_ni(rst_ni),
.d_i(state_i),
.q_o(state_raw)
);
assign state_o = StateEnumT'(state_raw);
@ -206,13 +206,13 @@ module fsm_auto (
end
my_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
);
endmodule
@ -240,13 +240,13 @@ module fsm_prim (
end
prim_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.d_i(state_d),
.q_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.d_i(state_d),
.q_o(state_q)
);
endmodule
@ -274,13 +274,13 @@ module fsm_prim_override (
end
prim_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.d_i(state_d),
.q_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.d_i(state_d),
.q_o(state_q)
);
endmodule
@ -308,14 +308,14 @@ module fsm_sparse_prim (
end
prim_sparse_fsm_flop #(
.StateEnumT(state_t),
.Width($bits(state_t)),
.ResetValue(S0)
.StateEnumT(state_t),
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
);
endmodule
@ -343,14 +343,14 @@ module fsm_sparse_prim_override (
end
prim_sparse_fsm_flop #(
.StateEnumT(state_t),
.Width($bits(state_t)),
.ResetValue(S0)
.StateEnumT(state_t),
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
);
endmodule
@ -378,13 +378,13 @@ module fsm_active_high (
end
active_high_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk(clk),
.rst(rst),
.d(state_d),
.q(state_q)
.clk(clk),
.rst(rst),
.d(state_d),
.q(state_q)
);
endmodule
@ -412,13 +412,13 @@ module fsm_active_high_rst_i (
end
active_high_rst_i_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk(clk),
.rst_i(rst),
.d(state_d),
.q(state_q)
.clk(clk),
.rst_i(rst),
.d(state_d),
.q(state_q)
);
endmodule
@ -445,11 +445,11 @@ module fsm_no_reset (
end
no_reset_fsm_flop #(
.Width($bits(state_t))
.Width($bits(state_t))
) u_state_regs (
.clk(clk),
.d(state_d),
.q(state_q)
.clk(clk),
.d(state_d),
.q(state_q)
);
endmodule
@ -477,12 +477,12 @@ module fsm_reset_no_param (
end
reset_no_param_fsm_flop #(
.Width($bits(state_t))
.Width($bits(state_t))
) u_state_regs (
.clk(clk),
.rst_n(rst_n),
.d(state_d),
.q(state_q)
.clk(clk),
.rst_n(rst_n),
.d(state_d),
.q(state_q)
);
endmodule
@ -510,13 +510,13 @@ module fsm_sync_reset_unknown_polarity (
end
sync_reset_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk(clk),
.my_reset(parent_reset),
.d(state_d),
.q(state_q)
.clk(clk),
.my_reset(parent_reset),
.d(state_d),
.q(state_q)
);
endmodule
@ -544,13 +544,13 @@ module fsm_custom_reset_parent_polarity (
end
custom_reset_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk(clk),
.my_reset(parent_reset),
.d(state_d),
.q(state_q)
.clk(clk),
.my_reset(parent_reset),
.d(state_d),
.q(state_q)
);
endmodule
@ -578,13 +578,13 @@ module fsm_custom_reset_active_high (
end
custom_reset_active_high_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk(clk),
.my_reset(parent_reset),
.d(state_d),
.q(state_q)
.clk(clk),
.my_reset(parent_reset),
.d(state_d),
.q(state_q)
);
endmodule
@ -612,11 +612,11 @@ module fsm_ambiguous_ignored (
end
ambiguous_fsm_flop u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.d_i(state_d),
.state_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.d_i(state_d),
.state_o(state_q)
);
endmodule
@ -644,13 +644,13 @@ module fsm_missing_reset_param (
end
my_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
);
endmodule
@ -684,13 +684,13 @@ module fsm_competing_direct (
end
my_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_state_regs (
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
.clk_i(clk),
.rst_ni(rst_n),
.state_i(state_d),
.state_o(state_q)
);
/* verilator lint_on BLKANDNBLK */
endmodule
@ -722,20 +722,78 @@ module t (
end
end
fsm_auto auto_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_prim prim_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_prim_override prim_override_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_sparse_prim sparse_prim_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_sparse_prim_override sparse_prim_override_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_active_high active_high_u (.clk(clk), .rst(rst), .start(start));
fsm_active_high_rst_i active_high_rst_i_u (.clk(clk), .rst(rst), .start(start));
fsm_no_reset no_reset_u (.clk(clk), .start(start));
fsm_reset_no_param reset_no_param_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_sync_reset_unknown_polarity sync_reset_u (.clk(clk), .parent_reset(rst), .start(start));
fsm_custom_reset_parent_polarity custom_reset_u (.clk(clk), .parent_reset(rst_n), .start(start));
fsm_auto auto_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_prim prim_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_prim_override prim_override_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_sparse_prim sparse_prim_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_sparse_prim_override sparse_prim_override_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_active_high active_high_u (
.clk(clk),
.rst(rst),
.start(start)
);
fsm_active_high_rst_i active_high_rst_i_u (
.clk(clk),
.rst(rst),
.start(start)
);
fsm_no_reset no_reset_u (
.clk(clk),
.start(start)
);
fsm_reset_no_param reset_no_param_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_sync_reset_unknown_polarity sync_reset_u (
.clk(clk),
.parent_reset(rst),
.start(start)
);
fsm_custom_reset_parent_polarity custom_reset_u (
.clk(clk),
.parent_reset(rst_n),
.start(start)
);
fsm_custom_reset_active_high custom_reset_active_high_u (
.clk(clk), .parent_reset(rst), .start(start));
fsm_ambiguous_ignored ambiguous_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_missing_reset_param missing_reset_u (.clk(clk), .rst_n(rst_n), .start(start));
fsm_competing_direct competing_u (.clk(clk), .rst_n(rst_n), .start(start));
.clk(clk),
.parent_reset(rst),
.start(start)
);
fsm_ambiguous_ignored ambiguous_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_missing_reset_param missing_reset_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
fsm_competing_direct competing_u (
.clk(clk),
.rst_n(rst_n),
.start(start)
);
endmodule

96
test_regress/t/t_fsm_register_wrapper_warn_bad.v
View File

@ -151,82 +151,82 @@ module t (
state_t missing_reset_connection_q;
odd_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_bad_simple (
.clk(clk),
.rst_n(rst_n),
.din(S0),
.dout(state_q)
.clk(clk),
.rst_n(rst_n),
.din(S0),
.dout(state_q)
);
missing_q_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_missing_q_port (
.clk(clk),
.rst_n(rst_n),
.din(missing_d),
.dout(missing_q)
.clk(clk),
.rst_n(rst_n),
.din(missing_d),
.dout(missing_q)
);
missing_clock_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_missing_clock_port (
.clk(clk),
.rst_n(rst_n),
.din(missing_clock_d),
.dout(missing_clock_q)
.clk(clk),
.rst_n(rst_n),
.din(missing_clock_d),
.dout(missing_clock_q)
);
partial_reset_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_partial_reset (
.clk(clk),
.rst_n(rst_n),
.din(partial_reset_d),
.dout(partial_reset_q)
.clk(clk),
.rst_n(rst_n),
.din(partial_reset_d),
.dout(partial_reset_q)
);
missing_reset_value_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_missing_reset_value (
.clk(clk),
.rst_n(rst_n),
.din(missing_reset_value_d),
.dout(missing_reset_value_q)
.clk(clk),
.rst_n(rst_n),
.din(missing_reset_value_d),
.dout(missing_reset_value_q)
);
value_no_reset_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_value_no_reset (
.clk(clk),
.rst_n(rst_n),
.din(value_no_reset_d),
.dout(value_no_reset_q)
.clk(clk),
.rst_n(rst_n),
.din(value_no_reset_d),
.dout(value_no_reset_q)
);
sync_reset_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_sync_reset (
.clk(clk),
.rst(rst),
.din(sync_reset_d),
.dout(sync_reset_q)
.clk(clk),
.rst(rst),
.din(sync_reset_d),
.dout(sync_reset_q)
);
missing_reset_connection_fsm_flop #(
.Width($bits(state_t)),
.ResetValue(S0)
.Width($bits(state_t)),
.ResetValue(S0)
) u_missing_reset_connection (
.clk(clk),
.rst_n(rst_n),
.din(missing_reset_connection_d),
.dout(missing_reset_connection_q)
.clk(clk),
.rst_n(rst_n),
.din(missing_reset_connection_d),
.dout(missing_reset_connection_q)
);
endmodule

59
test_regress/t/t_pull_bitsel.v
View File

@ -8,26 +8,48 @@
// for the assigns incorrectly covers all bits, causing the pull constant
// to be optimized away.
// verilog_format: off
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
// verilator lint_off PINMISSING
// Tie cell with pullup/pulldown (like sky130_fd_sc_hd__conb)
module conb(output HI, output LO);
pullup pu (HI);
module conb (
output HI,
output LO
);
pullup pu (HI);
pulldown pd (LO);
endmodule
// Wrapper that instantiates tie cell and connects to specific bit
module tiecell_1(output HI, output LO);
conb base (.HI(HI), .LO(LO));
module tiecell_1 (
output HI,
output LO
);
conb base (
.HI(HI),
.LO(LO)
);
endmodule
// Parameterized tie cell for ranged connections; exercises the multi-bit
// SEL path in V3Tristate's per-bit pull tracking.
module tiecell_n #(parameter N = 1) (output [N-1:0] HI, output [N-1:0] LO);
module tiecell_n #(
parameter N = 1
) (
output [N-1:0] HI,
output [N-1:0] LO
);
genvar gi;
generate
for (gi = 0; gi < N; gi = gi + 1) begin : g
conb base (.HI(HI[gi]), .LO(LO[gi]));
conb base (
.HI(HI[gi]),
.LO(LO[gi])
);
end
endgenerate
endmodule
@ -36,7 +58,9 @@ endmodule
// constants implemented as tie cells: each output bit driven by exactly one
// tie cell of fixed direction. Per-bit pulls must propagate up to the parent
// net the submodule's output port is connected to.
module mask_col(output [7:0] out);
module mask_col (
output [7:0] out
);
conb t0 (.HI(out[0])); // bit 0 = 1
conb t1 (.LO(out[1])); // bit 1 = 0
conb t2 (.HI(out[2])); // bit 2 = 1
@ -47,14 +71,17 @@ module mask_col(output [7:0] out);
conb t7 (.LO(out[7])); // bit 7 = 0
endmodule
module top(input [31:0] in_value, output [31:0] out_value);
module top (
input [31:0] in_value,
output [31:0] out_value
);
assign out_value[7:0] = in_value[7:0];
// Bits 8-15: bit 15 pulled up, rest pulled down via single-bit and ranged cells.
tiecell_1 u_hi (.HI(out_value[15]));
tiecell_n #(.N(4)) u_lo_8_11 (.LO(out_value[11:8]));
tiecell_1 u_lo_8_dup(.LO(out_value[8]));
tiecell_n #(.N(3)) u_lo_12_14(.LO(out_value[14:12]));
tiecell_1 u_hi (.HI(out_value[15]));
tiecell_n #(.N(4)) u_lo_8_11 (.LO(out_value[11:8]));
tiecell_1 u_lo_8_dup (.LO(out_value[8]));
tiecell_n #(.N(3)) u_lo_12_14 (.LO(out_value[14:12]));
// Bits 16-23 driven hierarchically through a part-select port connection.
mask_col u_mask (.out(out_value[23:16]));
@ -62,16 +89,16 @@ module top(input [31:0] in_value, output [31:0] out_value);
assign out_value[31:24] = in_value[31:24];
endmodule
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
module t;
// Use wire with assign - values propagate in same delta cycle
wire [31:0] in_value = 32'hDE00_0000;
wire [31:0] out_value;
top dut (.in_value(in_value), .out_value(out_value));
top dut (
.in_value(in_value),
.out_value(out_value)
);
// 0xDE = passthrough[31:24], 0x55 = mask_col HI/LO/HI/LO/HI/LO/HI/LO at [23:16],
// 0x80 = bit 15 pullup + bits 14:8 pulldown, 0x00 = passthrough[7:0].

6
test_regress/t/t_pull_bitsel_conflict_bad.out
View File

@ -1,6 +1,6 @@
%Error-UNSUPPORTED: t/t_pull_bitsel_conflict_bad.v:17:28: Conflicting pullup/pulldown direction on bit 2 of 'bus'
%Error-UNSUPPORTED: t/t_pull_bitsel_conflict_bad.v:22:23: Conflicting pullup/pulldown direction on bit 2 of 'bus'
: ... note: In instance 't'
17 | module t(output wire [3:0] bus);
| ^~~
22 | output wire [3:0] bus
| ^~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to

14
test_regress/t/t_pull_bitsel_conflict_bad.v
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@ -6,17 +6,23 @@
// verilator lint_off PINMISSING
module pullup_leaf(output wire o);
module pullup_leaf (
output wire o
);
pullup pu (o);
endmodule
module pulldown_leaf(output wire o);
module pulldown_leaf (
output wire o
);
pulldown pd (o);
endmodule
module t(output wire [3:0] bus);
module t (
output wire [3:0] bus
);
// Bit 2 of 'bus' is driven by both a pullup AND a pulldown through hierarchy,
// which is an electrical short. Verilator must reject this at compile time.
pullup_leaf pu_inst (.o(bus[2]));
pullup_leaf pu_inst (.o(bus[2]));
pulldown_leaf pd_inst (.o(bus[2]));
endmodule

43
test_regress/t/t_pull_bitsel_whole.v
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@ -5,12 +5,22 @@
// verilator lint_off PINMISSING
module conb(output HI, output LO);
pullup pu (HI);
// verilog_format: off
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module conb (
output HI,
output LO
);
pullup pu (HI);
pulldown pd (LO);
endmodule
module mask_col(output [7:0] out);
module mask_col (
output [7:0] out
);
conb t0 (.HI(out[0]));
conb t1 (.LO(out[1]));
conb t2 (.HI(out[2]));
@ -21,15 +31,19 @@ module mask_col(output [7:0] out);
conb t7 (.LO(out[7]));
endmodule
module pull_hi(output HI);
module pull_hi (
output HI
);
pullup pu (HI);
endmodule
module top(input [7:0] in_value, output [15:0] out_value, output [7:0] direct_mask,
output direct_pull);
typedef struct packed {
logic [1:0] field;
} pair_t;
module top (
input [7:0] in_value,
output [15:0] out_value,
output [7:0] direct_mask,
output direct_pull
);
typedef struct packed {logic [1:0] field;} pair_t;
wire [7:0] pulled;
pair_t pair;
@ -48,17 +62,18 @@ module top(input [7:0] in_value, output [15:0] out_value, output [7:0] direct_ma
pull_hi u_direct_pull (.HI(direct_pull));
endmodule
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
module t;
wire [7:0] in_value = 8'hA6;
wire [15:0] out_value;
wire [7:0] direct_mask;
wire direct_pull;
top dut (.in_value(in_value), .out_value(out_value), .direct_mask(direct_mask),
.direct_pull(direct_pull));
top dut (
.in_value(in_value),
.out_value(out_value),
.direct_mask(direct_mask),
.direct_pull(direct_pull)
);
initial begin
`checkh(out_value, 16'h55A6);

31
test_regress/t/t_tri_pullup_bus.v
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@ -8,22 +8,28 @@
// SPDX-FileCopyrightText: 2026 Lucas Amaral
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
`default_nettype none
module pullup_mod(output HI);
pullup pullup0(HI);
module pullup_mod (
output HI
);
pullup pullup0 (HI);
endmodule
module pulldown_mod(output LO);
pulldown pulldown0(LO);
module pulldown_mod (
output LO
);
pulldown pulldown0 (LO);
endmodule
module top (
input wire [3:0] in_value,
output wire [7:0] out_value
input wire [3:0] in_value,
output wire [7:0] out_value
);
// Lower 4 bits driven by input (partial SEL assign)
assign out_value[3:0] = in_value;
@ -33,17 +39,20 @@ module top (
// out_value[5] = 0 (pulldown)
// out_value[6] = 1 (pullup)
// out_value[7] = 0 (pulldown)
pullup_mod p0(.HI(out_value[4]));
pulldown_mod p1(.LO(out_value[5]));
pullup_mod p2(.HI(out_value[6]));
pulldown_mod p3(.LO(out_value[7]));
pullup_mod p0 (.HI(out_value[4]));
pulldown_mod p1 (.LO(out_value[5]));
pullup_mod p2 (.HI(out_value[6]));
pulldown_mod p3 (.LO(out_value[7]));
endmodule
module t;
reg [3:0] in_value;
wire [7:0] out_value;
top dut(.in_value(in_value), .out_value(out_value));
top dut (
.in_value(in_value),
.out_value(out_value)
);
initial begin
// Test 1: Lower bits = 0xF