Fix addition of data types to --xml.
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@ -1708,6 +1708,7 @@ public:
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virtual AstNodeDType* virtRefDTypep() const { return NULL; } // Iff has a non-null refDTypep(), as generic node function
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virtual void virtRefDTypep(AstNodeDType* nodep) { } // Iff has refDTypep(), set as generic node function
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virtual bool similarDType(AstNodeDType* samep) const = 0; // Assignable equivalence. Call skipRefp() on this and samep before calling
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virtual AstNodeDType* subDTypep() const { return NULL; } // Iff has a non-null subDTypep(), as generic node function
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//
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// Changing the width may confuse the data type resolution, so must clear TypeTable cache after use.
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void widthForce(int width, int sized) { m_width=width; m_widthMin=sized; }
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@ -1811,7 +1812,7 @@ public:
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AstNodeDType* getChildDTypep() const { return childDTypep(); }
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AstNodeDType* childDTypep() const { return op1p()->castNodeDType(); } // op1 = Range of variable
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void childDTypep(AstNodeDType* nodep) { setOp1p(nodep); }
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AstNodeDType* subDTypep() const { return m_refDTypep ? m_refDTypep : childDTypep(); }
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virtual AstNodeDType* subDTypep() const { return m_refDTypep ? m_refDTypep : childDTypep(); }
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void refDTypep(AstNodeDType* nodep) { m_refDTypep = nodep; }
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virtual AstNodeDType* virtRefDTypep() const { return m_refDTypep; }
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virtual void virtRefDTypep(AstNodeDType* nodep) { refDTypep(nodep); }
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@ -179,7 +179,7 @@ public:
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AstNodeDType* getChildDTypep() const { return childDTypep(); }
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AstNodeDType* childDTypep() const { return op1p()->castNodeDType(); } // op1 = Type assigning to
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void childDTypep(AstNodeDType* nodep) { setOp1p(nodep); }
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AstNodeDType* subDTypep() const { return dtypep() ? dtypep() : childDTypep(); }
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virtual AstNodeDType* subDTypep() const { return dtypep() ? dtypep() : childDTypep(); }
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virtual AstBasicDType* basicp() const { return subDTypep()->basicp(); } // (Slow) recurse down to find basic data type
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virtual AstNodeDType* skipRefp() const { return subDTypep()->skipRefp(); }
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virtual AstNodeDType* skipRefToConstp() const { return subDTypep()->skipRefToConstp(); }
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@ -217,7 +217,7 @@ public:
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AstNodeDType* getChildDTypep() const { return childDTypep(); }
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AstNodeDType* childDTypep() const { return op1p()->castNodeDType(); } // op1 = Type assigning to
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void childDTypep(AstNodeDType* nodep) { setOp1p(nodep); }
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AstNodeDType* subDTypep() const { return dtypep() ? dtypep() : childDTypep(); }
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virtual AstNodeDType* subDTypep() const { return dtypep() ? dtypep() : childDTypep(); }
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void addAttrsp(AstNode* nodep) { addNOp4p(nodep); }
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AstNode* attrsp() const { return op4p(); } // op4 = Attributes during early parse
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// METHODS
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@ -267,7 +267,7 @@ public:
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AstNodeDType* getChildDTypep() const { return childDTypep(); }
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AstNodeDType* childDTypep() const { return op1p()->castNodeDType(); } // op1 = Range of variable
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void childDTypep(AstNodeDType* nodep) { setOp1p(nodep); }
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AstNodeDType* subDTypep() const { return dtypep() ? dtypep() : childDTypep(); }
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virtual AstNodeDType* subDTypep() const { return dtypep() ? dtypep() : childDTypep(); }
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void* containerp() const { return m_containerp; }
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// METHODS
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AstNodeDType* dtypeSkipRefp() const { return dtypep()->skipRefp(); } // op1 = Range of variable
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@ -478,7 +478,7 @@ public:
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AstNodeDType* getChildDTypep() const { return childDTypep(); }
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AstNodeDType* childDTypep() const { return op1p()->castNodeDType(); } // op1 = Range of variable
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void childDTypep(AstNodeDType* nodep) { setOp1p(nodep); }
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AstNodeDType* subDTypep() const { return m_refDTypep ? m_refDTypep : childDTypep(); } // op1 = Range of variable
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virtual AstNodeDType* subDTypep() const { return m_refDTypep ? m_refDTypep : childDTypep(); } // op1 = Range of variable
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void refDTypep(AstNodeDType* nodep) { m_refDTypep = nodep; }
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virtual AstNodeDType* virtRefDTypep() const { return m_refDTypep; }
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virtual void virtRefDTypep(AstNodeDType* nodep) { refDTypep(nodep); }
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@ -588,7 +588,7 @@ public:
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void refDTypep(AstNodeDType* nodep) { m_refDTypep=nodep; }
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virtual AstNodeDType* virtRefDTypep() const { return refDTypep(); }
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virtual void virtRefDTypep(AstNodeDType* nodep) { refDTypep(nodep); }
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AstNodeDType* subDTypep() const { return m_refDTypep; }
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virtual AstNodeDType* subDTypep() const { return m_refDTypep; }
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AstPackage* packagep() const { return m_packagep; }
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void packagep(AstPackage* nodep) { m_packagep=nodep; }
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};
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@ -642,7 +642,7 @@ public:
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AstNodeDType* getChildDTypep() const { return childDTypep(); }
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AstNodeDType* childDTypep() const { return op1p()->castNodeDType(); } // op1 = Range of variable
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void childDTypep(AstNodeDType* nodep) { setOp1p(nodep); }
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AstNodeDType* subDTypep() const { return m_refDTypep ? m_refDTypep : childDTypep(); }
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virtual AstNodeDType* subDTypep() const { return m_refDTypep ? m_refDTypep : childDTypep(); }
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void refDTypep(AstNodeDType* nodep) { m_refDTypep = nodep; }
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virtual AstNodeDType* virtRefDTypep() const { return m_refDTypep; }
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virtual void virtRefDTypep(AstNodeDType* nodep) { refDTypep(nodep); }
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@ -738,7 +738,7 @@ public:
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AstNodeDType* getChildDTypep() const { return childDTypep(); }
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AstNodeDType* childDTypep() const { return op1p()->castNodeDType(); } // op1 = Data type
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void childDTypep(AstNodeDType* nodep) { setOp1p(nodep); }
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AstNodeDType* subDTypep() const { return m_refDTypep ? m_refDTypep : childDTypep(); } // op1 = Range of variable
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virtual AstNodeDType* subDTypep() const { return m_refDTypep ? m_refDTypep : childDTypep(); } // op1 = Range of variable
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void refDTypep(AstNodeDType* nodep) { m_refDTypep = nodep; }
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virtual AstNodeDType* virtRefDTypep() const { return m_refDTypep; }
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virtual void virtRefDTypep(AstNodeDType* nodep) { refDTypep(nodep); }
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@ -1103,7 +1103,7 @@ public:
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void addAttrsp(AstNode* nodep) { addNOp4p(nodep); }
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AstNode* attrsp() const { return op4p(); } // op4 = Attributes during early parse
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void childDTypep(AstNodeDType* nodep) { setOp1p(nodep); }
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AstNodeDType* subDTypep() const { return dtypep() ? dtypep() : childDTypep(); }
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virtual AstNodeDType* subDTypep() const { return dtypep() ? dtypep() : childDTypep(); }
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void attrClockEn(bool flag) { m_attrClockEn = flag; }
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void attrClocker(AstVarAttrClocker flag) { m_attrClocker = flag; }
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void attrFileDescr(bool flag) { m_fileDescr = flag; }
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@ -4911,7 +4911,7 @@ public:
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AstNodeDType* getChildDTypep() const { return childDTypep(); }
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AstNodeDType* childDTypep() const { return op1p()->castNodeDType(); } // op1 = Type assigning to
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void childDTypep(AstNodeDType* nodep) { setOp1p(nodep); }
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AstNodeDType* subDTypep() const { return dtypep() ? dtypep() : childDTypep(); }
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virtual AstNodeDType* subDTypep() const { return dtypep() ? dtypep() : childDTypep(); }
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AstNode* itemsp() const { return op2p(); } // op2 = AstPatReplicate, AstPatMember, etc
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};
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class AstPatMember : public AstNodeMath {
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@ -80,9 +80,9 @@ class EmitXmlFileVisitor : public AstNVisitor {
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if (nodep->name()!="") { puts(" name="); putsQuoted(nodep->prettyName()); }
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if (nodep->tag()!="") { puts(" tag="); putsQuoted(nodep->tag()); }
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if (AstNodeDType* dtp = nodep->castNodeDType()) {
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if (dtp->skipRefp() && dtp->skipRefp()!=dtp) { puts(" sub_dtype_id="); outputId(dtp->skipRefp()); }
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if (dtp->subDTypep()) { puts(" sub_dtype_id="); outputId(dtp->subDTypep()->skipRefp()); }
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} else {
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if (nodep->dtypep()) { puts(" dtype_id="); outputId(nodep->dtypep()); }
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if (nodep->dtypep()) { puts(" dtype_id="); outputId(nodep->dtypep()->skipRefp()); }
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}
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}
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void outputChildrenEnd(AstNode* nodep, string tag) {
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@ -127,7 +127,7 @@ class EmitXmlFileVisitor : public AstNVisitor {
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}
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virtual void visit(AstAssignW* nodep) {
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outputTag(nodep, "contassign"); // IEEE: vpiContAssign
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outputChildrenEnd(nodep, "contAssign");
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outputChildrenEnd(nodep, "contassign");
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}
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// Data types
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@ -0,0 +1,70 @@
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<?xml version="1.0" ?>
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<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
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<verilator_xml>
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<files>
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<file id="a" filename="AstRoot" language="1800-2012"/>
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<file id="b" filename="COMMAND_LINE" language="1800-2012"/>
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<file id="c" filename="INTERNAL_VERILATOR_DEFINE" language="1800-2012"/>
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<file id="d" filename="input.vc" language="1800-2012"/>
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<file id="e" filename="t/t_xml_first.v" language="1800-2012"/>
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</files>
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<netlist>
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<module fl="e6" name="t" topModule="1">
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<var fl="e12" name="clk" dtype_id="1"/>
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<var fl="e13" name="d" dtype_id="2"/>
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<var fl="e14" name="q" dtype_id="2"/>
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<var fl="e16" name="between" dtype_id="2"/>
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<instance fl="e18" name="cell1" defName="mod1">
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<port fl="e18" name="q" direction="out" portIndex="1">
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<varref fl="e18" name="between" dtype_id="2"/>
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</port>
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<port fl="e21" name="clk" direction="in" portIndex="2">
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<varref fl="e21" name="clk" dtype_id="1"/>
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</port>
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<port fl="e22" name="d" direction="in" portIndex="3">
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<varref fl="e22" name="d" dtype_id="2"/>
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</port>
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</instance>
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<instance fl="e24" name="cell2" defName="mod2">
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<port fl="e24" name="d" direction="in" portIndex="1">
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<varref fl="e24" name="between" dtype_id="2"/>
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</port>
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<port fl="e27" name="q" direction="out" portIndex="2">
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<varref fl="e27" name="q" dtype_id="2"/>
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</port>
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<port fl="e29" name="clk" direction="in" portIndex="3">
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<varref fl="e29" name="clk" dtype_id="1"/>
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</port>
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</instance>
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</module>
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<module fl="e33" name="mod1">
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<var fl="e35" name="clk" dtype_id="1"/>
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<var fl="e36" name="d" dtype_id="2"/>
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<var fl="e37" name="q" dtype_id="2"/>
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<always fl="e39">
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<sentree fl="e39">
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<senitem fl="e39">
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<varref fl="e39" name="clk" dtype_id="1"/>
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</senitem>
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</sentree>
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<assigndly fl="e40" dtype_id="2">
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<varref fl="e40" name="d" dtype_id="2"/>
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<varref fl="e40" name="q" dtype_id="2"/>
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</assigndly>
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</always>
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</module>
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<module fl="e44" name="mod2">
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<var fl="e46" name="clk" dtype_id="1"/>
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<var fl="e47" name="d" dtype_id="2"/>
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<var fl="e48" name="q" dtype_id="2"/>
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<contassign fl="e51" dtype_id="2">
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<varref fl="e51" name="d" dtype_id="2"/>
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<varref fl="e51" name="q" dtype_id="2"/>
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</contassign>
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</module>
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<typetable fl="a0">
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<basicdtype fl="e46" id="1" name="logic"/>
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<basicdtype fl="e13" id="2" name="logic" left="3" right="0"/>
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</typetable>
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</netlist>
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</verilator_xml>
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@ -16,7 +16,6 @@ compile (
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verilator_make_gcc => 0,
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);
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file_grep ($out_filename, qr/<verilator_xml>/);
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ok(1);
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ok(files_identical("$out_filename", "t/$Self->{name}.out"));
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1;
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@ -17,18 +17,25 @@
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<var fl="e23" name="this_struct" dtype_id="3"/>
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</module>
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<typetable fl="a0">
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<basicdtype fl="e23" id="4" name="logic" left="31" right="0"/>
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<basicdtype fl="e8" id="1" name="logic"/>
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<structdtype fl="e14" id="2">
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<memberdtype fl="e15" id="4" name="clk" tag="this is clk" sub_dtype_id="5"/>
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<memberdtype fl="e16" id="6" name="k" sub_dtype_id="7"/>
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<memberdtype fl="e17" id="8" name="enable" tag="enable" sub_dtype_id="9"/>
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<memberdtype fl="e18" id="10" name="data" tag="data" sub_dtype_id="11"/>
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<memberdtype fl="e15" id="5" name="clk" tag="this is clk" sub_dtype_id="6"/>
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<memberdtype fl="e16" id="7" name="k" sub_dtype_id="8"/>
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<memberdtype fl="e17" id="9" name="enable" tag="enable" sub_dtype_id="10"/>
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<memberdtype fl="e18" id="11" name="data" tag="data" sub_dtype_id="12"/>
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</structdtype>
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<basicdtype fl="e15" id="5" name="logic"/>
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<basicdtype fl="e16" id="7" name="logic"/>
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<basicdtype fl="e17" id="9" name="logic"/>
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<basicdtype fl="e18" id="11" name="logic"/>
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<refdtype fl="e23" id="3" name="my_struct" sub_dtype_id="2"/>
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<basicdtype fl="e15" id="6" name="logic"/>
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<basicdtype fl="e16" id="8" name="logic"/>
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<basicdtype fl="e17" id="10" name="logic"/>
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<basicdtype fl="e18" id="12" name="logic"/>
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<unpackarraydtype fl="e23" id="3" sub_dtype_id="2">
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<range fl="e23">
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<const fl="e23" name="32'h1" dtype_id="4"/>
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<const fl="e23" name="32'h0" dtype_id="4"/>
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</range>
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</unpackarraydtype>
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<refdtype fl="e23" id="13" name="my_struct" sub_dtype_id="2"/>
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</typetable>
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</netlist>
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</verilator_xml>
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@ -20,6 +20,6 @@ module m
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// This is a comment
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my_struct this_struct;
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my_struct this_struct [2];
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endmodule
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