[#74021] remove code related to SAIF file rollover
This commit is contained in:
Mateusz Gancarz
parent
b426a7145d
commit
c024ff0836
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@ -121,68 +121,15 @@ void VerilatedSaif::open(const char* filename) VL_MT_SAFE_EXCLUDES(m_mutex) {
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if (isOpen()) return;
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// Set member variables
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m_filename = filename; // "" is ok, as someone may overload open
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m_filename = filename; // "" is ok, as someone may overload open
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openNextImp(m_rolloverSize != 0);
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if (!isOpen()) return;
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m_currentTimeOrigin = m_totalTime;
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initializeSaifFileContents();
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Super::traceInit();
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// When using rollover, the first chunk contains the header only.
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if (m_rolloverSize) openNextImp(true);
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}
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void VerilatedSaif::openNext(bool incFilename) VL_MT_SAFE_EXCLUDES(m_mutex) {
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// Open next filename in concat sequence, mangle filename if
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// incFilename is true.
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const VerilatedLockGuard lock{m_mutex};
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openNextImp(incFilename);
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}
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void VerilatedSaif::openNextImp(bool incFilename) {
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closePrev(); // Close existing
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if (incFilename) {
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// Find _0000.{ext} in filename
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std::string name = m_filename;
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const size_t pos = name.rfind('.');
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if (pos > 8 && 0 == std::strncmp("_cat", name.c_str() + pos - 8, 4)
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&& std::isdigit(name.c_str()[pos - 4]) && std::isdigit(name.c_str()[pos - 3])
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&& std::isdigit(name.c_str()[pos - 2]) && std::isdigit(name.c_str()[pos - 1])) {
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// Increment code.
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if ((++(name[pos - 1])) > '9') {
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name[pos - 1] = '0';
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if ((++(name[pos - 2])) > '9') {
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name[pos - 2] = '0';
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if ((++(name[pos - 3])) > '9') {
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name[pos - 3] = '0';
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if ((++(name[pos - 4])) > '9') { //
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name[pos - 4] = '0';
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}
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}
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}
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}
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} else {
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// Append _cat0000
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name.insert(pos, "_cat0000");
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}
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m_filename = name;
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}
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if (VL_UNCOVERABLE(m_filename[0] == '|')) {
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assert(0); // LCOV_EXCL_LINE // Not supported yet.
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} else {
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// cppcheck-suppress duplicateExpression
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if (!m_filep->open(m_filename)) {
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// User code can check isOpen()
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m_isOpen = false;
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return;
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}
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}
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m_isOpen = true;
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constDump(true); // First dump must containt the const signals
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fullDump(true); // First dump must be full
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// noop, SAIF only needs one file per trace
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}
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void VerilatedSaif::initializeSaifFileContents() {
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@ -198,11 +145,10 @@ void VerilatedSaif::initializeSaifFileContents() {
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}
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bool VerilatedSaif::preChangeDump() {
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if (VL_UNLIKELY(m_rolloverSize)) openNextImp(true);
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return isOpen();
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}
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void VerilatedSaif::emitTimeChange(uint64_t timeui) { m_totalTime = timeui; }
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void VerilatedSaif::emitTimeChange(uint64_t timeui) { m_time = timeui; }
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VerilatedSaif::~VerilatedSaif() {
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close();
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@ -164,7 +164,6 @@ private:
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bool m_fileNewed; // m_filep needs destruction
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bool m_isOpen = false; // True indicates open file
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std::string m_filename; // Filename we're writing to (if open)
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uint64_t m_rolloverSize = 0; // File size to rollover at
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int m_indent = 0; // indentation size in spaces
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@ -175,15 +174,14 @@ private:
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std::unordered_map<uint32_t, VerilatedSaifActivityVar> m_activity; // map of variables codes mapped to their activity objects
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std::vector<std::vector<VerilatedSaifActivityBit>> m_activityArena; // memory pool for signals bits objects
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uint64_t m_totalTime{0}; // total time of the currently traced simulation
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uint64_t m_currentTimeOrigin{0};
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uint64_t m_time{0}; // total time of the currently traced simulation
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// stack of declared scopes combined names
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std::vector<std::pair<std::string, VerilatedTracePrefixType>> m_prefixStack{
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{"", VerilatedTracePrefixType::SCOPE_MODULE}};
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// METHODS
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VL_ATTR_ALWINLINE uint64_t currentTime() const { return m_totalTime - m_currentTimeOrigin; }
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VL_ATTR_ALWINLINE uint64_t currentTime() const { return m_time; }
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void initializeSaifFileContents();
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void finalizeSaifFileContents();
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@ -204,7 +202,6 @@ private:
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void clearCurrentlyCollectedData();
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void openNextImp(bool incFilename);
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void closePrev();
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void closeErr();
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void declare(uint32_t code, const char* name, const char* wirep, bool array, int arraynum,
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@ -241,7 +238,7 @@ public:
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// ACCESSORS
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// Set size in bytes after which new file should be created.
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void rolloverSize(uint64_t size) VL_MT_SAFE { m_rolloverSize = size; }
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void rolloverSize(uint64_t size) VL_MT_SAFE { /* noop */ }
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// METHODS - All must be thread safe
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// Open the file; call isOpen() to see if errors
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@ -380,12 +377,9 @@ public:
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/// The header is only in the first file created, this allows
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/// "cat" to be used to combine the header plus any number of data files.
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void openNext(bool incFilename = true) VL_MT_SAFE { m_sptrace.openNext(incFilename); }
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/// Set size in bytes after which new file should be created
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/// This will create a header file, followed by each separate file
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/// which might be larger than the given size (due to chunking and
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/// alignment to a start of a given time's dump). Any file but the
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/// first may be removed. Cat files together to create viewable saif.
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void rolloverSize(size_t size) VL_MT_SAFE { m_sptrace.rolloverSize(size); }
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void rolloverSize(size_t size) VL_MT_SAFE { /* noop */ }
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/// Close dump
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void close() VL_MT_SAFE {
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m_sptrace.close();
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@ -1,56 +0,0 @@
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// -*- mode: C++; c-file-style: "cc-mode" -*-
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//
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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#include <verilated.h>
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#include <verilated_saif_c.h>
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#include <memory>
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#include VM_PREFIX_INCLUDE
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unsigned long long main_time = 0;
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double sc_time_stamp() { return (double)main_time; }
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const char* trace_name() {
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static char name[1000];
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VL_SNPRINTF(name, 1000, VL_STRINGIFY(TEST_OBJ_DIR) "/simpart_%04d.saif", (int)main_time);
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return name;
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}
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int main(int argc, char** argv) {
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Verilated::debug(0);
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Verilated::traceEverOn(true);
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Verilated::commandArgs(argc, argv);
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std::unique_ptr<VM_PREFIX> top{new VM_PREFIX{"top"}};
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std::unique_ptr<VerilatedSaifC> tfp{new VerilatedSaifC};
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top->trace(tfp.get(), 99);
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tfp->open(trace_name());
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top->clk = 0;
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while (main_time < 190) { // Creates 2 files
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top->clk = !top->clk;
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top->eval();
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if ((main_time % 100) == 0) {
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tfp->close();
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tfp->open(trace_name());
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}
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tfp->dump((unsigned int)(main_time));
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++main_time;
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}
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tfp->close();
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top->final();
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tfp.reset();
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top.reset();
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printf("*-* All Finished *-*\n");
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return 0;
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}
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@ -1,25 +0,0 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt_all')
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test.top_filename = "t/t_trace_cat_fst.v"
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test.compile(make_top_shell=False,
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make_main=False,
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v_flags2=["--trace-saif --exe", test.pli_filename])
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test.execute()
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test.saif_identical(test.obj_dir + "/simpart_0000.saif", "t/" + test.name + "_0000.out")
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test.saif_identical(test.obj_dir + "/simpart_0100.saif", "t/" + test.name + "_0100.out")
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test.passes()
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@ -1,29 +0,0 @@
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(SAIFILE
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(SAIFVERSION "2.0")
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(DIRECTION "backward")
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(DESIGN "foo")
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(PROGRAM_NAME "Verilator")
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(VERSION "5.032")
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(DIVIDER / )
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(TIMESCALE 1ps)
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(DURATION 99)
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(INSTANCE top
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(NET
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(clk (T0 49) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 100))
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)
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(INSTANCE t
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(NET
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(clk (T0 49) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 100))
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(cyc\[0\] (T0 50) (T1 49) (TZ 0) (TX 0) (TB 0) (TC 49))
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(cyc\[1\] (T0 51) (T1 48) (TZ 0) (TX 0) (TB 0) (TC 24))
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(cyc\[2\] (T0 51) (T1 48) (TZ 0) (TX 0) (TB 0) (TC 12))
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(cyc\[3\] (T0 51) (T1 48) (TZ 0) (TX 0) (TB 0) (TC 6))
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(cyc\[4\] (T0 64) (T1 35) (TZ 0) (TX 0) (TB 0) (TC 3))
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(cyc\[5\] (T0 64) (T1 35) (TZ 0) (TX 0) (TB 0) (TC 1))
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(unchanged\[1\] (T0 0) (T1 99) (TZ 0) (TX 0) (TB 0) (TC 1))
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(unchanged\[3\] (T0 0) (T1 99) (TZ 0) (TX 0) (TB 0) (TC 1))
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(unchanged\[5\] (T0 0) (T1 99) (TZ 0) (TX 0) (TB 0) (TC 1))
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)
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)
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)
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)
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@ -1,30 +0,0 @@
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(SAIFILE
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(SAIFVERSION "2.0")
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(DIRECTION "backward")
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(DESIGN "foo")
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(PROGRAM_NAME "Verilator")
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(VERSION "5.032")
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(DIVIDER / )
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(TIMESCALE 1ps)
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(DURATION 90)
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(INSTANCE top
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(NET
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(clk (T0 45) (T1 45) (TZ 0) (TX 0) (TB 0) (TC 90))
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)
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(INSTANCE t
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(NET
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(clk (T0 45) (T1 45) (TZ 0) (TX 0) (TB 0) (TC 90))
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(cyc\[0\] (T0 46) (T1 44) (TZ 0) (TX 0) (TB 0) (TC 44))
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(cyc\[1\] (T0 45) (T1 45) (TZ 0) (TX 0) (TB 0) (TC 23))
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(cyc\[2\] (T0 45) (T1 45) (TZ 0) (TX 0) (TB 0) (TC 11))
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(cyc\[3\] (T0 45) (T1 45) (TZ 0) (TX 0) (TB 0) (TC 5))
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(cyc\[4\] (T0 33) (T1 57) (TZ 0) (TX 0) (TB 0) (TC 3))
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(cyc\[5\] (T0 62) (T1 28) (TZ 0) (TX 0) (TB 0) (TC 2))
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(cyc\[6\] (T0 29) (T1 61) (TZ 0) (TX 0) (TB 0) (TC 1))
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(unchanged\[1\] (T0 1) (T1 89) (TZ 0) (TX 0) (TB 0) (TC 1))
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(unchanged\[3\] (T0 1) (T1 89) (TZ 0) (TX 0) (TB 0) (TC 1))
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(unchanged\[5\] (T0 1) (T1 89) (TZ 0) (TX 0) (TB 0) (TC 1))
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)
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)
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)
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)
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