Fix `--trace-max-width` and increase to 4096. (#2385).

Changes

@@ -38,6 +38,7 @@ Verilator 5.041 devel
 * Optimize duplicate 'if' and '?:' conditions (#3807) (#6495)
 * Optimize dead functions in more cases (#6380) (#6430). [Artur Bieniek, Antmicro Ltd.]
 * Optimize constant folding in wide expression expansion (#6381). [Geza Lore]
+* Fix `--trace-max-width` and increase to 4096. (#2385).
 * Fix missing BLKSEQ when connecting module port to array (#2973).
 * Fix LATCH warning with CASEINCOMPLETE (#3301).
 * Fix unused parameterized class causing internal error (#4013). [Alberto Del Rio]

docs/guide/exe_verilator.rst

@@ -1668,14 +1668,15 @@ Summary:
 .. option:: --trace-max-array <depth>
 
    Rarely needed.  Specify the maximum array depth of a signal that may be
-   traced.  Defaults to 32, as tracing large arrays may greatly slow traced
-   simulations.
+   traced.  Zero allows any width. Defaults to 32, as tracing large arrays
+   may greatly slow traced simulations.
 
 .. option:: --trace-max-width <width>
 
-   Rarely needed.  Specify the maximum bit width of a signal that may be
-   traced.  Defaults to 256, as tracing large vectors may greatly slow
-   traced simulations.
+   Rarely needed.  Specify the maximum total bit width of a signal, across
+   all elements if an array, that may be traced.  Zero allows any width.
+   Defaults to 4096, as tracing large vectors may greatly slow traced
+   simulations.
 
 .. option:: --no-trace-params
 

src/V3Options.h

@@ -341,7 +341,7 @@ private:
     VTimescale  m_timeOverrideUnit;  // main switch: --timescale-override
     int         m_traceDepth = 0;   // main switch: --trace-depth
     int         m_traceMaxArray = 32;  // main switch: --trace-max-array
-    int         m_traceMaxWidth = 256; // main switch: --trace-max-width
+    int         m_traceMaxWidth = 4096; // main switch: --trace-max-width
     int         m_traceThreads = 0; // main switch: --trace-threads
     int         m_unrollCount = 64;  // main switch: --unroll-count
     int         m_unrollStmts = 30000;  // main switch: --unroll-stmts

src/V3TraceDecl.cpp

@@ -170,23 +170,30 @@ class TraceDeclVisitor final : public VNVisitor {
 
     // METHODS
 
-    const char* vscIgnoreTrace(const AstVarScope* nodep) {
+    string vscIgnoreTrace(const AstVarScope* nodep) {
         // Return true if this shouldn't be traced
         // See also similar rule in V3Coverage::varIgnoreToggle
         const AstVar* const varp = nodep->varp();
-        if (!varp->isTrace()) {
-            return "Verilator trace_off";
-        } else if (!nodep->isTrace()) {
-            return "Verilator instance trace_off";
-        } else {
-            const string prettyName = nodep->prettyName();
-            if (!v3Global.opt.traceUnderscore()) {
-                if (!prettyName.empty() && prettyName[0] == '_') return "Leading underscore";
-                if (prettyName.find("._") != string::npos) return "Inlined leading underscore";
-            }
-            if (!V3Control::getScopeTraceOn(prettyName)) return "Vlt scope trace_off";
+        if (!varp->isTrace()) return "Verilator trace_off";
+        if (!nodep->isTrace()) return "Verilator instance trace_off";
+
+        const int width = recurseDTypeWidth(nodep->varp()->dtypep());
+        if (v3Global.opt.traceMaxWidth() && width > v3Global.opt.traceMaxWidth())
+            return "Width " + cvtToStr(width) + " > --trace-max-width";
+
+        const string prettyName = nodep->prettyName();
+        if (!V3Control::getScopeTraceOn(prettyName)) return "Vlt scope trace_off";
+        if (!v3Global.opt.traceUnderscore()) {
+            if (!prettyName.empty() && prettyName[0] == '_') return "Leading underscore";
+            if (prettyName.find("._") != string::npos) return "Inlined leading underscore";
         }
-        return nullptr;
+        return ""s;
+    }
+
+    int recurseDTypeWidth(const AstNodeDType* nodep) {
+        if (const AstNodeArrayDType* adtypep = VN_CAST(nodep, NodeArrayDType))
+            return recurseDTypeWidth(adtypep->subDTypep()) * adtypep->declRange().elements();
+        return nodep->width();
     }
 
     AstCFunc* newCFunc(FileLine* flp, const string& name) {
@@ -245,7 +252,7 @@ class TraceDeclVisitor final : public VNVisitor {
         addToSubFunc(newp);
     }
 
-    void addIgnore(const char* why) {
+    void addIgnore(const string& why) {
         ++m_statIgnSigs;
         std::string cmt = "Tracing: "s + m_traName + " // Ignored: " + why;
         if (debug() > 3 && m_traVscp) std::cout << "- " << m_traVscp->fileline() << cmt << endl;
@@ -403,8 +410,9 @@ class TraceDeclVisitor final : public VNVisitor {
                 if (AstVarScope* const vscp = entry.vscp()) {
                     // This is a signal: build AstTraceDecl for it
                     m_traVscp = vscp;
-                    if (const char* const ignoreReasonp = vscIgnoreTrace(m_traVscp)) {
-                        addIgnore(ignoreReasonp);
+                    const string& ignoreReason = vscIgnoreTrace(m_traVscp);
+                    if (!ignoreReason.empty()) {
+                        addIgnore(ignoreReason);
                     } else {
                         ++m_statSigs;
                         // Create reference to whole signal. We will operate on this during the
@@ -514,7 +522,8 @@ class TraceDeclVisitor final : public VNVisitor {
         // Note more specific dtypes above
         if (!m_traVscp) return;
 
-        if (static_cast<int>(nodep->arrayUnpackedElements()) > v3Global.opt.traceMaxArray()) {
+        if (v3Global.opt.traceMaxArray()
+            && static_cast<int>(nodep->arrayUnpackedElements()) > v3Global.opt.traceMaxArray()) {
             addIgnore("Wide memory > --trace-max-array ents");
             return;
         }

test_regress/t/t_trace_array.py

@@ -11,7 +11,7 @@ import vltest_bootstrap
 
 test.scenarios('simulator')
 
-test.compile(verilator_flags2=['--cc --trace-vcd --trace-structs'])
+test.compile(verilator_flags2=['--cc --trace-vcd --trace-structs --trace-max-width 0'])
 
 test.execute()
 

test_regress/t/t_trace_array.v

@@ -11,7 +11,7 @@ module t (clk);
    // Trace would overflow at 256KB which is 256 kb dump, 16 kb in a chunk
 
    typedef struct packed {
-      logic [1024*1024:0] d;
+      logic [128*1024:0] d;
    } s1_t; // 128 b
 
    s1_t biggie;

test_regress/t/t_trace_array_fst.py

@@ -12,7 +12,7 @@ import vltest_bootstrap
 test.scenarios('vlt')
 test.top_filename = "t/t_trace_array.v"
 
-test.compile(verilator_flags2=['--cc --trace-fst --trace-structs'])
+test.compile(verilator_flags2=['--cc --trace-fst --trace-structs --trace-max-width 0'])
 
 test.execute()
 

test_regress/t/t_trace_array_fst_portable.py

@@ -13,7 +13,9 @@ test.scenarios('vlt')
 test.top_filename = "t/t_trace_array.v"
 test.golden_filename = "t/t_trace_array_fst.out"
 
-test.compile(verilator_flags2=['--cc --trace-fst --trace-structs', '-CFLAGS -DVL_PORTABLE_ONLY'])
+test.compile(verilator_flags2=[
+    '--cc --trace-fst --trace-structs --trace-max-width 0', '-CFLAGS -DVL_PORTABLE_ONLY'
+])
 
 test.execute()
 

test_regress/t/t_trace_array_fst_portable_sc.py

@@ -16,7 +16,9 @@ test.golden_filename = "t/t_trace_array_fst_sc.out"
 if not test.have_sc:
     test.skip("No SystemC installed")
 
-test.compile(verilator_flags2=['--sc --trace-fst --trace-structs', '-CFLAGS -DVL_PORTABLE_ONLY'])
+test.compile(verilator_flags2=[
+    '--sc --trace-fst --trace-structs --trace-max-width 0', '-CFLAGS -DVL_PORTABLE_ONLY'
+])
 
 test.execute()
 

test_regress/t/t_trace_array_fst_sc.py

@@ -15,7 +15,7 @@ test.top_filename = "t/t_trace_array.v"
 if not test.have_sc:
     test.skip("No SystemC installed")
 
-test.compile(verilator_flags2=['--sc --trace-fst --trace-structs'])
+test.compile(verilator_flags2=['--sc --trace-fst --trace-structs --trace-max-width 0'])
 
 test.execute()
 

test_regress/t/t_trace_array_fst_threads_1.py

@@ -13,7 +13,8 @@ test.scenarios('vlt')
 test.top_filename = "t/t_trace_array.v"
 test.golden_filename = "t/t_trace_array_fst.out"
 
-test.compile(verilator_flags2=['--cc --trace-fst --trace-threads 1 --trace-structs'])
+test.compile(
+    verilator_flags2=['--cc --trace-fst --trace-threads 1 --trace-structs --trace-max-width 0'])
 
 test.execute()
 

test_regress/t/t_trace_array_fst_threads_1_sc.py

@@ -16,7 +16,8 @@ test.golden_filename = "t/t_trace_array_fst_sc.out"
 if not test.have_sc:
     test.skip("No SystemC installed")
 
-test.compile(verilator_flags2=['--sc --trace-fst --trace-threads 1 --trace-structs'])
+test.compile(
+    verilator_flags2=['--sc --trace-fst --trace-threads 1 --trace-structs --trace-max-width 0'])
 
 test.execute()
 

test_regress/t/t_trace_array_fst_threads_2.py

@@ -13,7 +13,8 @@ test.scenarios('vlt')
 test.top_filename = "t/t_trace_array.v"
 test.golden_filename = "t/t_trace_array_fst.out"
 
-test.compile(verilator_flags2=['--cc --trace-fst --trace-threads 2 --trace-structs'])
+test.compile(
+    verilator_flags2=['--cc --trace-fst --trace-threads 2 --trace-structs --trace-max-width 0'])
 
 test.execute()
 

test_regress/t/t_trace_array_fst_threads_2_sc.py

@@ -16,7 +16,8 @@ test.golden_filename = "t/t_trace_array_fst_sc.out"
 if not test.have_sc:
     test.skip("No SystemC installed")
 
-test.compile(verilator_flags2=['--sc --trace-fst --trace-threads 2 --trace-structs'])
+test.compile(
+    verilator_flags2=['--sc --trace-fst --trace-threads 2 --trace-structs --trace-max-width 0'])
 
 test.execute()
 

test_regress/t/t_trace_array_saif.py

@@ -13,7 +13,7 @@ test.scenarios('vlt')
 test.top_filename = "t/t_trace_array.v"
 test.golden_filename = "t/t_trace_array_saif.out"
 
-test.compile(verilator_flags2=['--cc --trace-saif --trace-structs'])
+test.compile(verilator_flags2=['--cc --trace-saif --trace-structs --trace-max-width 0'])
 
 test.execute()
 

test_regress/t/t_trace_array_saif_portable.py

@@ -13,7 +13,10 @@ test.scenarios('vlt')
 test.top_filename = "t/t_trace_array.v"
 test.golden_filename = "t/t_trace_array_saif.out"
 
-test.compile(verilator_flags2=['--cc --trace-saif --trace-structs', '-CFLAGS -DVL_PORTABLE_ONLY'])
+# Don't pass  --trace-max-width 0, we shrink the file intentionally
+test.compile(verilator_flags2=[
+    '--cc --trace-saif --trace-structs --trace-max-width 0', '-CFLAGS -DVL_PORTABLE_ONLY'
+])
 
 test.execute()
 

test_regress/t/t_trace_array_saif_threads_1.py

@@ -13,7 +13,8 @@ test.scenarios('vlt')
 test.top_filename = "t/t_trace_array.v"
 test.golden_filename = "t/t_trace_array_saif.out"
 
-test.compile(verilator_flags2=['--cc --trace-saif --trace-threads 1 --trace-structs'])
+test.compile(
+    verilator_flags2=['--cc --trace-saif --trace-threads 1 --trace-structs --trace-max-width 0'])
 
 test.execute()
 

test_regress/t/t_trace_array_saif_threads_2.py

@@ -13,7 +13,8 @@ test.scenarios('vlt')
 test.top_filename = "t/t_trace_array.v"
 test.golden_filename = "t/t_trace_array_saif.out"
 
-test.compile(verilator_flags2=['--cc --trace-saif --trace-threads 2 --trace-structs'])
+test.compile(
+    verilator_flags2=['--cc --trace-saif --trace-threads 2 --trace-structs --trace-max-width 0'])
 
 test.execute()
 

test_regress/t/t_trace_array_threads_1.py

@@ -13,7 +13,8 @@ test.scenarios('vlt')
 test.top_filename = "t/t_trace_array.v"
 test.golden_filename = "t/t_trace_array.out"
 
-test.compile(verilator_flags2=['--cc --trace-vcd --trace-threads 1 --trace-structs'])
+test.compile(
+    verilator_flags2=['--cc --trace-vcd --trace-threads 1 --trace-structs --trace-max-width 0'])
 
 test.execute()
 

test_regress/t/t_trace_max.out

@@ -0,0 +1,43 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module top $end
+  $var wire 1 # clk $end
+  $scope module t $end
+   $var wire 1 # clk $end
+   $var wire 32 $ cyc [31:0] $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+0#
+b00000000000000000000000000000000 $
+#10
+1#
+b00000000000000000000000000000001 $
+#15
+0#
+#20
+1#
+b00000000000000000000000000000010 $
+#25
+0#
+#30
+1#
+b00000000000000000000000000000011 $
+#35
+0#
+#40
+1#
+b00000000000000000000000000000100 $
+#45
+0#
+#50
+1#
+b00000000000000000000000000000101 $
+#55
+0#
+#60
+1#
+b00000000000000000000000000000110 $

test_regress/t/t_trace_max.py

@@ -0,0 +1,24 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.compile(verilator_flags2=["--cc --trace-vcd --trace-max-width 64 --trace-max-array 16"])
+
+test.execute()
+
+test.file_grep_not(test.trace_filename, r'wide1')
+test.file_grep_not(test.trace_filename, r'wide2')
+test.file_grep_not(test.trace_filename, r'deep1')
+
+test.vcd_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

test_regress/t/t_trace_max.v

@@ -0,0 +1,27 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (
+    input clk
+);
+
+  int cyc;
+
+  logic [95:0] wide1;
+  logic [15:0] wide2[16];  // 256 bits
+  logic deep1[24];
+
+  always @(posedge clk) begin
+    wide1[31:0] = cyc;
+    wide2[2] = cyc[15:0];
+    deep1[3] = cyc[0];
+    cyc <= cyc + 1;
+    if (cyc == 5) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+    end
+  end
+endmodule

test_regress/t/t_trace_max_default.out

@@ -0,0 +1,140 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module top $end
+  $var wire 1 O clk $end
+  $scope module t $end
+   $var wire 1 O clk $end
+   $var wire 32 # cyc [31:0] $end
+   $var wire 96 $ wide1 [95:0] $end
+   $var wire 16 ' wide2[0] [15:0] $end
+   $var wire 16 ( wide2[1] [15:0] $end
+   $var wire 16 ) wide2[2] [15:0] $end
+   $var wire 16 * wide2[3] [15:0] $end
+   $var wire 16 + wide2[4] [15:0] $end
+   $var wire 16 , wide2[5] [15:0] $end
+   $var wire 16 - wide2[6] [15:0] $end
+   $var wire 16 . wide2[7] [15:0] $end
+   $var wire 16 / wide2[8] [15:0] $end
+   $var wire 16 0 wide2[9] [15:0] $end
+   $var wire 16 1 wide2[10] [15:0] $end
+   $var wire 16 2 wide2[11] [15:0] $end
+   $var wire 16 3 wide2[12] [15:0] $end
+   $var wire 16 4 wide2[13] [15:0] $end
+   $var wire 16 5 wide2[14] [15:0] $end
+   $var wire 16 6 wide2[15] [15:0] $end
+   $var wire 1 7 deep1[0] $end
+   $var wire 1 8 deep1[1] $end
+   $var wire 1 9 deep1[2] $end
+   $var wire 1 : deep1[3] $end
+   $var wire 1 ; deep1[4] $end
+   $var wire 1 < deep1[5] $end
+   $var wire 1 = deep1[6] $end
+   $var wire 1 > deep1[7] $end
+   $var wire 1 ? deep1[8] $end
+   $var wire 1 @ deep1[9] $end
+   $var wire 1 A deep1[10] $end
+   $var wire 1 B deep1[11] $end
+   $var wire 1 C deep1[12] $end
+   $var wire 1 D deep1[13] $end
+   $var wire 1 E deep1[14] $end
+   $var wire 1 F deep1[15] $end
+   $var wire 1 G deep1[16] $end
+   $var wire 1 H deep1[17] $end
+   $var wire 1 I deep1[18] $end
+   $var wire 1 J deep1[19] $end
+   $var wire 1 K deep1[20] $end
+   $var wire 1 L deep1[21] $end
+   $var wire 1 M deep1[22] $end
+   $var wire 1 N deep1[23] $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 #
+b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $
+b0000000000000000 '
+b0000000000000000 (
+b0000000000000000 )
+b0000000000000000 *
+b0000000000000000 +
+b0000000000000000 ,
+b0000000000000000 -
+b0000000000000000 .
+b0000000000000000 /
+b0000000000000000 0
+b0000000000000000 1
+b0000000000000000 2
+b0000000000000000 3
+b0000000000000000 4
+b0000000000000000 5
+b0000000000000000 6
+07
+08
+09
+0:
+0;
+0<
+0=
+0>
+0?
+0@
+0A
+0B
+0C
+0D
+0E
+0F
+0G
+0H
+0I
+0J
+0K
+0L
+0M
+0N
+0O
+#10
+b00000000000000000000000000000001 #
+1O
+#15
+0O
+#20
+b00000000000000000000000000000010 #
+b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 $
+b0000000000000001 )
+1:
+1O
+#25
+0O
+#30
+b00000000000000000000000000000011 #
+b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 $
+b0000000000000010 )
+0:
+1O
+#35
+0O
+#40
+b00000000000000000000000000000100 #
+b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 $
+b0000000000000011 )
+1:
+1O
+#45
+0O
+#50
+b00000000000000000000000000000101 #
+b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 $
+b0000000000000100 )
+0:
+1O
+#55
+0O
+#60
+b00000000000000000000000000000110 #
+b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $
+b0000000000000101 )
+1:
+1O

test_regress/t/t_trace_max_default.py

@@ -0,0 +1,25 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+test.top_filename = "t/t_trace_max.v"
+
+test.compile(verilator_flags2=["--cc --trace-vcd"])
+
+test.execute()
+
+test.file_grep(test.trace_filename, r'wide1')
+test.file_grep(test.trace_filename, r'wide2')
+test.file_grep(test.trace_filename, r'deep1')
+
+test.vcd_identical(test.trace_filename, test.golden_filename)
+
+test.passes()