Fix missing assignment for wide unpacked structs (#4233)
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@ -73,6 +73,7 @@ Jiuyang Liu
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Joey Liu
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John Coiner
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John Demme
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Jiamin Zhu
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Jonathan Drolet
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Jose Loyola
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Joseph Nwabueze
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@ -354,6 +354,7 @@ public:
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&& !VN_IS(nodep->rhsp(), CMethodHard) //
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&& !VN_IS(nodep->rhsp(), VarRef) //
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&& !VN_IS(nodep->rhsp(), AssocSel) //
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&& !VN_IS(nodep->rhsp(), StructSel) //
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&& !VN_IS(nodep->rhsp(), ArraySel)) {
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// Wide functions assign into the array directly, don't need separate assign statement
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m_wideTempRefp = VN_AS(nodep->lhsp(), VarRef);
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@ -0,0 +1,22 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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verilator_flags2 => [ '-DWIDE_WIDTH=128' ],
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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@ -0,0 +1,29 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Jomit626.
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// SPDX-License-Identifier: CC0-1.0
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`ifndef WIDE_WIDTH
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`define WIDE_WIDTH 128
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`endif
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module t ();
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typedef struct {
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bit [`WIDE_WIDTH-1:0] data;
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} wide_t;
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logic [`WIDE_WIDTH-1:0] ldata;
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wide_t wide_0;
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initial begin
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wide_0.data = `WIDE_WIDTH'hda7ada7a;
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ldata = wide_0.data;
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if (ldata != `WIDE_WIDTH'hda7ada7a)
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$stop();
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$write("*-* All Finished *-*\n");
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$finish();
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end
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endmodule
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