Add UNSUPPORTED on dotted disable instead of syntax error
This commit is contained in:
parent
d4bb58630e
commit
bf5cbb512e
|
|
@ -3559,8 +3559,10 @@ statement_item<nodep>: // IEEE: statement_item
|
||||||
//
|
//
|
||||||
// // IEEE: disable_statement
|
// // IEEE: disable_statement
|
||||||
| yDISABLE yFORK ';' { $$ = new AstDisableFork{$1}; }
|
| yDISABLE yFORK ';' { $$ = new AstDisableFork{$1}; }
|
||||||
| yDISABLE idAny/*hierarchical_identifier-task_or_block*/ ';'
|
| yDISABLE idAny/*UNSUP: hierarchical_identifier-task_or_block*/ ';'
|
||||||
{ $$ = new AstDisable{$1, *$2}; }
|
{ $$ = new AstDisable{$1, *$2}; }
|
||||||
|
| yDISABLE idAny '.' idDotted ';'
|
||||||
|
{ $$ = nullptr; BBUNSUP($4, "Unsupported: disable with '.'"); }
|
||||||
// // IEEE: event_trigger
|
// // IEEE: event_trigger
|
||||||
| yP_MINUSGT idDotted/*hierarchical_identifier-event*/ ';'
|
| yP_MINUSGT idDotted/*hierarchical_identifier-event*/ ';'
|
||||||
{ $$ = new AstFireEvent{$1, $2, false}; }
|
{ $$ = new AstFireEvent{$1, $2, false}; }
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,5 @@
|
||||||
|
%Error-UNSUPPORTED: t/t_for_disable_dot.v:14:35: Unsupported: disable with '.'
|
||||||
|
14 | if (i == 5) disable t.named;
|
||||||
|
| ^~~~~
|
||||||
|
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
|
||||||
|
%Error: Exiting due to
|
||||||
|
|
@ -0,0 +1,19 @@
|
||||||
|
#!/usr/bin/env perl
|
||||||
|
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||||
|
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||||
|
#
|
||||||
|
# Copyright 2003 by Wilson Snyder. This program is free software; you
|
||||||
|
# can redistribute it and/or modify it under the terms of either the GNU
|
||||||
|
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||||
|
# Version 2.0.
|
||||||
|
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||||
|
|
||||||
|
scenarios(linter => 1);
|
||||||
|
|
||||||
|
lint(
|
||||||
|
fails => $Self->{vlt_all},
|
||||||
|
expect_filename => $Self->{golden_filename},
|
||||||
|
);
|
||||||
|
|
||||||
|
ok(1);
|
||||||
|
1;
|
||||||
|
|
@ -0,0 +1,22 @@
|
||||||
|
// DESCRIPTION: Verilator: Verilog Test module
|
||||||
|
//
|
||||||
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||||
|
// any use, without warranty, 2023 by Wilson Snyder.
|
||||||
|
// SPDX-License-Identifier: CC0-1.0
|
||||||
|
|
||||||
|
module t (/*AUTOARG*/);
|
||||||
|
|
||||||
|
int i;
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
begin : named
|
||||||
|
for (i = 0; i < 10; ++i) begin : loop
|
||||||
|
if (i == 5) disable t.named;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
if (i != 5) $stop;
|
||||||
|
$write("*-* All Finished *-*\n");
|
||||||
|
$finish;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
Loading…
Reference in New Issue