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Support V-AMS wreal

This commit is contained in:
Wilson Snyder 2011-11-27 10:31:06 -05:00
parent b9e67157c6
commit bedf946fb2
4 changed files with 18 additions and 2 deletions
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2
bin/verilator
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@ -1700,7 +1700,7 @@ languages.
AMS parsing is enabled with "--language VAMS" or "--language 1800+VAMS".
At present Verilator implements ceil, exp, floor, ln, log, pow, sqrt,
and string.
string, and wreal.
=head2 Sugar/PSL Support

2
src/verilog.l
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@ -627,7 +627,7 @@ word [a-zA-Z0-9_]+
"transition" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"units" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"white_noise" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"wreal" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"wreal" { FL; return yWREAL; }
"zi_nd" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"zi_np" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }
"zi_zd" { yyerrorf("Unsupported: AMS reserved word not implemented: %s",yytext); }

3
src/verilog.y
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@ -380,6 +380,7 @@ class AstSenTree;
%token<fl> yVOID "void"
%token<fl> yWHILE "while"
%token<fl> yWIRE "wire"
%token<fl> yWREAL "wreal"
%token<fl> yXNOR "xnor"
%token<fl> yXOR "xor"
@ -1087,6 +1088,8 @@ non_integer_type<bdtypep>: // ==IEEE: non_integer_type
yREAL { $$ = new AstBasicDType($1,AstBasicDTypeKwd::DOUBLE); }
| yREALTIME { $$ = new AstBasicDType($1,AstBasicDTypeKwd::DOUBLE); }
//UNSUP ySHORTREAL { $$ = new AstBasicDType($1,AstBasicDTypeKwd::FLOAT); }
// // VAMS - somewhat hackish
| yWREAL { $$ = new AstBasicDType($1,AstBasicDTypeKwd::DOUBLE); VARDECL(WIRE); }
;
signingE<signstate>: // IEEE: signing - plus empty

13
test_regress/t/t_vams_basic.v
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@ -20,6 +20,11 @@ module t (/*AUTOARG*/
end
endtask
wreal wr;
assign wr = 1.1;
sub sub (.*);
initial begin
check(`__LINE__, sqrt(2.0) , 1.414);
check(`__LINE__, pow(2.0,2.0) , 4.0);
@ -32,3 +37,11 @@ module t (/*AUTOARG*/
$finish;
end
endmodule
module sub (
input wreal wr
);
initial begin
if (wr != 1.1) $stop;
end
endmodule