Fix time import error on time parameters (#5786).

Changes

@@ -13,7 +13,7 @@ Verilator 5.033 devel
 
 **Major:**
 
-* Add expression coverage (#5719). [Todd Strader]
+* Add expression coverage (#4677) (#5719). [Todd Strader]
 
 **Minor:**
 
@@ -56,6 +56,7 @@ Verilator 5.033 devel
 * Fix VFileContent reference count (#5769) (#5771). [Dave Sargeant]
 * Fix ignoring joins in stringify in preprocessor (#5777). [Krzysztof Bieganski, Antmicro Ltd.]
 * Fix unpacked split_var (#5782) (#5785). [Yutetsu TAKATSUKASA]
+* Fix time import error on time parameters (#5786). [Luca Colagrande]
 * Fix matching language extension options including dots.
 
 

src/V3LinkParse.cpp

@@ -718,6 +718,7 @@ class LinkParseVisitor final : public VNVisitor {
             nodep->name(newName);
             nodep->origName(newName);
         }
+        iterateChildren(nodep);
     }
     void visit(AstGenCase* nodep) override {
         ++m_genblkNum;

test_regress/t/t_time_param.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=['--binary'])
+
+test.execute()
+
+test.passes()

test_regress/t/t_time_param.v

@@ -0,0 +1,39 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`timescale 1ns/1ps
+
+module vip_snitch_cluster
+  #(parameter realtime ClkPeriod = 10ns)
+  (output logic clk_o);
+
+   initial begin
+      forever begin
+         clk_o = 1;
+         #(ClkPeriod/2);
+         clk_o = 0;
+         #(ClkPeriod/2);
+      end
+   end
+
+   initial begin
+      #(ClkPeriod*100);
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule
+
+module t;
+    logic clk;
+
+    vip_snitch_cluster #(
+        .ClkPeriod(1ns)
+    ) vip (
+        .clk_o(clk)
+    );
+
+endmodule