regression in my large design
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@ -480,13 +480,13 @@ class UndrivenVisitor final : public VNVisitorConst {
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// EOM
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//&& entryp->getNodep()) {
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&& (entryp->getNodep()
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|| (V3UndrivenCapture::enableWriteSummary && entryp->getCallNodep()))) {
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|| (m_enableWriteSummary && entryp->getCallNodep()))) {
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// EOM
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const AstNode* const otherWritep
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= entryp->getNodep()
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? static_cast<const AstNode*>(entryp->getNodep())
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: (V3UndrivenCapture::enableWriteSummary ? entryp->getCallNodep()
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: (m_enableWriteSummary ? entryp->getCallNodep()
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: nullptr);
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if (m_alwaysCombp
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@ -69,7 +69,13 @@ private:
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UINFO(DBG, "UndrivenCapture: direct write in "
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<< taskNameQ(m_curTaskp) << " var=" << nodep->varp()->prettyNameQ()
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<< " at " << nodep->fileline());
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m_cap.info(m_curTaskp).directWrites.push_back(nodep->varp());
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//m_cap.info(m_curTaskp).directWrites.push_back(nodep->varp());
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AstVar* const retVarp = VN_CAST(m_curTaskp->fvarp(), Var);
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if (retVarp && nodep->varp() == retVarp) {
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// Skip: function return variable is local, not a side-effect
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} else {
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m_cap.info(m_curTaskp).directWrites.push_back(nodep->varp());
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}
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}
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iterateChildrenConst(nodep);
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}
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(verilator_flags2=["--binary"])
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test.execute()
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test.passes()
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@ -0,0 +1,37 @@
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// DESCRIPTION: Verilator: MULTIDRIVEN false positive - package function return var
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//
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// Minimal reproducer for: package function with "return expr" used in always_comb expression.
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// The function return variable must not be treated as a side-effect "writeSummary" target.
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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package p;
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function automatic int num_bytes(input int size);
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return 1 << size;
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endfunction
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endpackage
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module t;
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typedef struct packed {
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logic [31:0] addr;
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logic [2:0] size;
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} meta_t;
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meta_t rd_meta_q;
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meta_t rd_meta;
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always_comb begin
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rd_meta = rd_meta_q;
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rd_meta.addr = rd_meta_q.addr + p::num_bytes(int'(rd_meta_q.size));
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end
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initial begin
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rd_meta_q.addr = 32'h100;
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rd_meta_q.size = 3'd2; // num_bytes = 4
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#1;
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`checkd(rd_meta.addr, 32'h104);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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