regression in my large design

This commit is contained in:
em2machine 2025-12-22 08:59:38 +01:00
parent 939dbb1fec
commit bde2a829ea
4 changed files with 64 additions and 3 deletions

View File

@ -480,13 +480,13 @@ class UndrivenVisitor final : public VNVisitorConst {
// EOM
//&& entryp->getNodep()) {
&& (entryp->getNodep()
|| (V3UndrivenCapture::enableWriteSummary && entryp->getCallNodep()))) {
|| (m_enableWriteSummary && entryp->getCallNodep()))) {
// EOM
const AstNode* const otherWritep
= entryp->getNodep()
? static_cast<const AstNode*>(entryp->getNodep())
: (V3UndrivenCapture::enableWriteSummary ? entryp->getCallNodep()
: (m_enableWriteSummary ? entryp->getCallNodep()
: nullptr);
if (m_alwaysCombp

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@ -69,7 +69,13 @@ private:
UINFO(DBG, "UndrivenCapture: direct write in "
<< taskNameQ(m_curTaskp) << " var=" << nodep->varp()->prettyNameQ()
<< " at " << nodep->fileline());
m_cap.info(m_curTaskp).directWrites.push_back(nodep->varp());
//m_cap.info(m_curTaskp).directWrites.push_back(nodep->varp());
AstVar* const retVarp = VN_CAST(m_curTaskp->fvarp(), Var);
if (retVarp && nodep->varp() == retVarp) {
// Skip: function return variable is local, not a side-effect
} else {
m_cap.info(m_curTaskp).directWrites.push_back(nodep->varp());
}
}
iterateChildrenConst(nodep);
}

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@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile(verilator_flags2=["--binary"])
test.execute()
test.passes()

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@ -0,0 +1,37 @@
// DESCRIPTION: Verilator: MULTIDRIVEN false positive - package function return var
//
// Minimal reproducer for: package function with "return expr" used in always_comb expression.
// The function return variable must not be treated as a side-effect "writeSummary" target.
`define stop $stop
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
package p;
function automatic int num_bytes(input int size);
return 1 << size;
endfunction
endpackage
module t;
typedef struct packed {
logic [31:0] addr;
logic [2:0] size;
} meta_t;
meta_t rd_meta_q;
meta_t rd_meta;
always_comb begin
rd_meta = rd_meta_q;
rd_meta.addr = rd_meta_q.addr + p::num_bytes(int'(rd_meta_q.size));
end
initial begin
rd_meta_q.addr = 32'h100;
rd_meta_q.size = 3'd2; // num_bytes = 4
#1;
`checkd(rd_meta.addr, 32'h104);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule