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https://github.com/verilator/verilator.git
synced 2026-10-06 10:03:44 +02:00
Support clocking blocks (#3674)
This commit is contained in:
Krzysztof Bieganski
+222
-15
@@ -16,6 +16,7 @@
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// Pre steps:
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// Attach clocks to each assertion
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// Substitute property references by property body (IEEE Std 1800-2012, section 16.12.1).
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// Transform clocking blocks into imperative logic
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//*************************************************************************
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#include "config_build.h"
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@@ -24,8 +25,10 @@
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#include "V3AssertPre.h"
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#include "V3Ast.h"
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#include "V3Const.h"
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#include "V3Global.h"
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#include "V3Task.h"
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#include "V3UniqueNames.h"
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VL_DEFINE_DEBUG_FUNCTIONS;
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@@ -37,16 +40,26 @@ class AssertPreVisitor final : public VNVisitor {
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// Eventually inlines calls to sequences, properties, etc.
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// We're not parsing the tree, or anything more complicated.
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private:
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// NODE STATE/TYPES
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// NODE STATE
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const VNUser1InUse m_inuser1;
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// STATE
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// Current context:
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AstNetlist* const m_netlistp = nullptr; // Current netlist
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AstNodeModule* m_modp = nullptr; // Current module
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AstClocking* m_clockingp = nullptr; // Current clocking block
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// Reset each module:
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AstSenItem* m_seniDefaultp = nullptr; // Default sensitivity (from AstDefClock)
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AstClocking* m_defaultClockingp = nullptr; // Default clocking for the current module
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// Reset each assertion:
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AstSenItem* m_senip = nullptr; // Last sensitivity
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// Reset each always:
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AstSenItem* m_seniAlwaysp = nullptr; // Last sensitivity in always
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// Reset each assertion:
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AstNodeExpr* m_disablep = nullptr; // Last disable
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// Other:
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V3UniqueNames m_cycleDlyNames{"__VcycleDly"}; // Cycle delay counter name generator
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bool m_inAssign = false; // True if in an AssignNode
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bool m_inAssignDlyLhs = false; // True if in AssignDly's LHS
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bool m_inSynchDrive = false; // True if in synchronous drive
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// METHODS
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@@ -55,7 +68,7 @@ private:
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// Return nullptr for always
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AstSenTree* newp = nullptr;
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AstSenItem* senip = m_senip;
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if (!senip) senip = m_seniDefaultp;
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if (!senip && m_defaultClockingp) senip = m_defaultClockingp->sensesp();
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if (!senip) senip = m_seniAlwaysp;
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if (!senip) {
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nodep->v3warn(E_UNSUPPORTED, "Unsupported: Unclocked assertion");
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@@ -139,17 +152,199 @@ private:
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// VISITORS
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//========== Statements
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void visit(AstClocking* nodep) override {
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void visit(AstClocking* const nodep) override {
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VL_RESTORER(m_clockingp);
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m_clockingp = nodep;
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UINFO(8, " CLOCKING" << nodep << endl);
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// Store the new default clock, reset on new module
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m_seniDefaultp = nodep->sensesp();
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// Trash it, keeping children
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if (nodep->bodysp()) {
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nodep->replaceWith(nodep->bodysp()->unlinkFrBack());
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} else {
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nodep->unlinkFrBack();
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iterateChildren(nodep);
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}
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void visit(AstClockingItem* const nodep) override {
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FileLine* const flp = nodep->fileline();
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V3Const::constifyEdit(nodep->skewp());
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if (!VN_IS(nodep->skewp(), Const)) {
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nodep->skewp()->v3error("Skew must be constant (IEEE 1800-2017 14.4)");
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VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
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return;
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}
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AstConst* const skewp = VN_AS(nodep->skewp(), Const);
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if (skewp->num().isNegative()) skewp->v3error("Skew cannot be negative");
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AstNodeExpr* const exprp = nodep->exprp();
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// Get a ref to the sampled/driven variable
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AstVar* const varp = nodep->varp()->unlinkFrBack();
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m_clockingp->addVarsp(varp);
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varp->user1p(nodep);
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if (nodep->direction() == VDirection::OUTPUT) {
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AstVarRef* const skewedRefp = new AstVarRef{flp, varp, VAccess::READ};
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skewedRefp->user1(true);
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AstAssign* const assignp = new AstAssign{flp, exprp->cloneTree(false), skewedRefp};
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if (skewp->isZero()) {
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// Drive the var in Re-NBA (IEEE 1800-2017 14.16)
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m_clockingp->addNextHere(new AstAlwaysReactive{
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flp, new AstSenTree{flp, m_clockingp->sensesp()->cloneTree(false)}, assignp});
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} else if (skewp->fileline()->timingOn()) {
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// Create a fork so that this AlwaysObserved can be retriggered before the
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// assignment happens. Also then it can be combo, avoiding the need for creating
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// new triggers.
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AstFork* const forkp = new AstFork{flp, "", assignp};
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forkp->joinType(VJoinType::JOIN_NONE);
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// Use Observed for this to make sure we do not miss the event
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m_clockingp->addNextHere(new AstAlwaysObserved{
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flp, new AstSenTree{flp, m_clockingp->sensesp()->cloneTree(false)}, forkp});
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if (v3Global.opt.timing().isSetTrue()) {
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assignp->timingControlp(new AstDelay{flp, skewp->unlinkFrBack(), false});
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} else if (v3Global.opt.timing().isSetFalse()) {
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nodep->v3warn(E_NOTIMING,
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"Clocking output skew greater than #0 requires --timing");
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} else {
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nodep->v3warn(E_NEEDTIMINGOPT,
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"Use --timing or --no-timing to specify how "
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"clocking output skew greater than #0 should be handled");
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}
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}
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} else if (nodep->direction() == VDirection::INPUT) {
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// Ref to the clockvar
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AstVarRef* const refp = new AstVarRef{flp, varp, VAccess::WRITE};
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refp->user1(true);
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if (skewp->num().is1Step()) {
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// Assign the sampled expression to the clockvar (IEEE 1800-2017 14.13)
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AstSampled* const sampledp = new AstSampled{flp, exprp->cloneTree(false)};
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sampledp->dtypeFrom(exprp);
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m_clockingp->addNextHere(new AstAssignW{flp, refp, sampledp});
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} else if (skewp->isZero()) {
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// #0 means the var has to be sampled in Observed (IEEE 1800-2017 14.13)
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AstAssign* const assignp = new AstAssign{flp, refp, exprp->cloneTree(false)};
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m_clockingp->addNextHere(new AstAlwaysObserved{
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flp, new AstSenTree{flp, m_clockingp->sensesp()->cloneTree(false)}, assignp});
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} else {
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// Create a queue where we'll store sampled values with timestamps
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AstSampleQueueDType* const queueDtp
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= new AstSampleQueueDType{flp, exprp->dtypep()};
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m_netlistp->typeTablep()->addTypesp(queueDtp);
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AstVar* const queueVarp = new AstVar{
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flp, VVarType::MODULETEMP,
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"__Vqueue__" + m_clockingp->name() + "__DOT__" + varp->name(), queueDtp};
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m_clockingp->addNextHere(queueVarp);
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// Create a process like this:
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// always queue.push(<sampled var>);
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AstCMethodHard* const pushp = new AstCMethodHard{
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flp, new AstVarRef{flp, queueVarp, VAccess::WRITE}, "push",
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new AstTime(nodep->fileline(), m_modp->timeunit())};
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pushp->addPinsp(exprp->cloneTree(false));
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pushp->dtypeSetVoid();
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m_clockingp->addNextHere(
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new AstAlways{flp, VAlwaysKwd::ALWAYS, nullptr, pushp->makeStmt()});
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// Create a process like this:
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// always @<clocking event> queue.pop(<skew>, /*out*/<skewed var>});
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AstCMethodHard* const popp = new AstCMethodHard{
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flp, new AstVarRef{flp, queueVarp, VAccess::READWRITE}, "pop",
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new AstTime(nodep->fileline(), m_modp->timeunit())};
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popp->addPinsp(skewp->unlinkFrBack());
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popp->addPinsp(refp);
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popp->dtypeSetVoid();
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m_clockingp->addNextHere(
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new AstAlways{flp, VAlwaysKwd::ALWAYS,
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new AstSenTree{flp, m_clockingp->sensesp()->cloneTree(false)},
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popp->makeStmt()});
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}
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} else {
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nodep->v3fatal("Invalid direction");
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}
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pushDeletep(nodep->unlinkFrBack());
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}
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void visit(AstDelay* nodep) override {
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// Only cycle delays are relevant in this stage; also only process once
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if (!nodep->isCycleDelay()) {
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if (m_inSynchDrive) {
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nodep->v3error("Only cycle delays can be used in synchronous drives"
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" (IEEE 1800-2017 14.16)");
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}
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return;
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}
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if (m_inAssign && !m_inSynchDrive) {
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nodep->v3error("Cycle delays not allowed as intra-assignment delays"
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" (IEEE 1800-2017 14.11)");
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VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
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return;
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}
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if (nodep->stmtsp()) nodep->addNextHere(nodep->stmtsp()->unlinkFrBackWithNext());
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FileLine* const flp = nodep->fileline();
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AstNodeExpr* valuep = V3Const::constifyEdit(nodep->lhsp()->unlinkFrBack());
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AstConst* const constp = VN_CAST(valuep, Const);
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if (constp->isZero()) {
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nodep->v3warn(E_UNSUPPORTED, "Unsupported: ##0 delays");
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VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
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return;
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}
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if (!m_defaultClockingp) {
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nodep->v3error("Usage of cycle delays requires default clocking"
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" (IEEE 1800-2017 14.11)");
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VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
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return;
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}
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AstEventControl* const controlp = new AstEventControl{
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nodep->fileline(),
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new AstSenTree{flp, m_defaultClockingp->sensesp()->cloneTree(false)}, nullptr};
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const std::string delayName = m_cycleDlyNames.get(nodep);
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AstVar* const cntVarp = new AstVar{flp, VVarType::BLOCKTEMP, delayName + "__counter",
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nodep->findBasicDType(VBasicDTypeKwd::UINT32)};
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AstBegin* const beginp = new AstBegin{flp, delayName + "__block", cntVarp, false, true};
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beginp->addStmtsp(new AstAssign{flp, new AstVarRef{flp, cntVarp, VAccess::WRITE}, valuep});
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beginp->addStmtsp(new AstWhile{
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nodep->fileline(),
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new AstGt{flp, new AstVarRef{flp, cntVarp, VAccess::READ}, new AstConst{flp, 0}},
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controlp,
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new AstAssign{flp, new AstVarRef{flp, cntVarp, VAccess::WRITE},
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new AstSub{flp, new AstVarRef{flp, cntVarp, VAccess::READ},
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new AstConst{flp, 1}}}});
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nodep->replaceWith(beginp);
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VL_DO_DANGLING(nodep->deleteTree(), nodep);
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}
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void visit(AstSenTree* nodep) override {
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if (m_inSynchDrive) {
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nodep->v3error("Event controls cannot be used in "
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"synchronous drives (IEEE 1800-2017 14.16)");
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}
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}
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void visit(AstNodeVarRef* nodep) override {
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if (AstClockingItem* const itemp = VN_CAST(nodep->varp()->user1p(), ClockingItem)) {
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if (nodep->access().isReadOrRW() && !nodep->user1()
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&& itemp->direction() == VDirection::OUTPUT) {
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nodep->v3error("Cannot read from output clockvar (IEEE 1800-2017 14.3)");
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}
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if (nodep->access().isWriteOrRW()) {
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if (itemp->direction() == VDirection::OUTPUT) {
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if (!m_inAssignDlyLhs) {
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nodep->v3error("Only non-blocking assignments can write "
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"to clockvars (IEEE 1800-2017 14.16)");
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}
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if (m_inAssign) m_inSynchDrive = true;
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} else if (!nodep->user1() && itemp->direction() == VDirection::INPUT) {
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nodep->v3error("Cannot write to input clockvar (IEEE 1800-2017 14.3)");
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}
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}
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}
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}
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void visit(AstNodeAssign* nodep) override {
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if (nodep->user1()) return;
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VL_RESTORER(m_inAssign);
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VL_RESTORER(m_inSynchDrive);
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m_inAssign = true;
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m_inSynchDrive = false;
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{
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VL_RESTORER(m_inAssignDlyLhs);
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m_inAssignDlyLhs = VN_IS(nodep, AssignDly);
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iterate(nodep->lhsp());
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}
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iterate(nodep->rhsp());
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if (nodep->timingControlp()) {
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iterate(nodep->timingControlp());
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} else if (m_inSynchDrive) {
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AstAssign* const assignp = new AstAssign{
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nodep->fileline(), nodep->lhsp()->unlinkFrBack(), nodep->rhsp()->unlinkFrBack()};
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assignp->user1(true);
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nodep->replaceWith(assignp);
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VL_DO_DANGLING(nodep->deleteTree(), nodep);
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}
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VL_DO_DANGLING(pushDeletep(nodep), nodep);
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}
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void visit(AstAlways* nodep) override {
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iterateAndNextNull(nodep->sensesp());
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@@ -255,9 +450,20 @@ private:
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VL_DO_DANGLING(pushDeletep(nodep), nodep);
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}
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void visit(AstNodeModule* nodep) override {
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VL_RESTORER(m_defaultClockingp);
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VL_RESTORER(m_modp);
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m_defaultClockingp = nullptr;
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nodep->foreach([&](AstClocking* const clockingp) {
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if (clockingp->isDefault()) {
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if (m_defaultClockingp) {
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clockingp->v3error("Only one default clocking block allowed per module"
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" (IEEE 1800-2017 14.12)");
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}
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m_defaultClockingp = clockingp;
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}
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});
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m_modp = nodep;
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iterateChildren(nodep);
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// Reset defaults
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m_seniDefaultp = nullptr;
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}
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void visit(AstProperty* nodep) override {
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// The body will be visited when will be substituted in place of property reference
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@@ -268,7 +474,8 @@ private:
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public:
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// CONSTRUCTORS
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explicit AssertPreVisitor(AstNetlist* nodep) {
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explicit AssertPreVisitor(AstNetlist* nodep)
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: m_netlistp{nodep} {
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clearAssertInfo();
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// Process
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iterate(nodep);
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