Tests: Fix up duplicate var declarations.

examples/tracing_c/top.v

@@ -14,18 +14,18 @@ module top
    input         fastclk,
    input         reset_l,
 
-   output [1:0]  out_small,
+   output wire [1:0]  out_small,
-   output [39:0] out_quad,
+   output wire [39:0] out_quad,
-   output [69:0] out_wide,
+   output wire [69:0] out_wide,
    input [1:0]   in_small,
    input [39:0]  in_quad,
    input [69:0]  in_wide
    );
 
    // Connect up the outputs, using some trivial logic
-   wire [1:0]    out_small = ~reset_l ? '0 : (in_small + 2'b1);
+   assign out_small = ~reset_l ? '0 : (in_small + 2'b1);
-   wire [39:0]   out_quad  = ~reset_l ? '0 : (in_quad + 40'b1);
+   assign out_quad  = ~reset_l ? '0 : (in_quad + 40'b1);
-   wire [69:0]   out_wide  = ~reset_l ? '0 : (in_wide + 70'b1);
+   assign out_wide  = ~reset_l ? '0 : (in_wide + 70'b1);
 
    // And an example sub module. The submodule will print stuff.
    sub sub (/*AUTOINST*/

examples/tracing_sc/top.v

@@ -14,18 +14,18 @@ module top
    input         fastclk,
    input         reset_l,
 
-   output [1:0]  out_small,
+   output wire [1:0]  out_small,
-   output [39:0] out_quad,
+   output wire [39:0] out_quad,
-   output [69:0] out_wide,
+   output wire [69:0] out_wide,
    input [1:0]   in_small,
    input [39:0]  in_quad,
    input [69:0]  in_wide
    );
 
    // Connect up the outputs, using some trivial logic
-   wire [1:0]    out_small = ~reset_l ? '0 : (in_small + 2'b1);
+   assign out_small = ~reset_l ? '0 : (in_small + 2'b1);
-   wire [39:0]   out_quad  = ~reset_l ? '0 : (in_quad + 40'b1);
+   assign out_quad  = ~reset_l ? '0 : (in_quad + 40'b1);
-   wire [69:0]   out_wide  = ~reset_l ? '0 : (in_wide + 70'b1);
+   assign out_wide  = ~reset_l ? '0 : (in_wide + 70'b1);
 
    // And an example sub module. The submodule will print stuff.
    sub sub (/*AUTOINST*/

test_regress/t/t_cdc_async_bad.v

@@ -77,5 +77,5 @@ endmodule
 
 module Sub (input a, b,
             output z);
-   wire            z = a|b;
+   assign z = a|b;
 endmodule

test_regress/t/t_func_outp.v

@@ -47,9 +47,9 @@ endmodule // mytop
 
 module inv(
              input [ 7:0 ]  a,
-             output  [ 7:0 ]  z
+             output wire [ 7:0 ]  z
              );
-   wire [7:0] 		      z = ~a;
+   assign z = ~a;
 endmodule
 
 
@@ -57,11 +57,10 @@ module ftest(
              input [ 7:0 ]  a,
                             b,   // Test legal syntax
              input clk,
-             output  [ 7:0 ]  z
+             output reg [ 7:0 ]  z
              );
 
    wire [7:0] 		      zi;
-   reg [7:0] 		      z;
 
    inv u1 (.a(myadd(a,b)),
 	   .z(zi));

test_regress/t/t_inst_array.v

@@ -55,5 +55,5 @@ endmodule
 
 module sub (input [7:0] allbits, input [1:0] onebit, output bitout);
    `INLINE_MODULE
-   wire bitout = (^ onebit) ^ (^ allbits);
+   assign bitout = (^ onebit) ^ (^ allbits);
 endmodule

test_regress/t/t_inst_array_bad.v

@@ -25,5 +25,5 @@ module t (/*AUTOARG*/
 endmodule
 
 module sub (input [7:0] allbits, input onebit, output bitout);
-   wire bitout = onebit ^ (^ allbits);
+   assign bitout = onebit ^ (^ allbits);
 endmodule

test_regress/t/t_inst_ccall.v

@@ -45,10 +45,10 @@ endmodule
 module sub (input [7:0] narrow, input [63:0] quad, output [31:0] longout, output [63:0] quadout);
    // verilator public_module
 `ifdef verilator
-   wire [31:0] longout = $c32("(",narrow,"+1)");
+   assign longout = $c32("(",narrow,"+1)");
-   wire [63:0] quadout = $c64("(",quad,"+1)");
+   assign quadout = $c64("(",quad,"+1)");
 `else
-   wire [31:0] longout = narrow + 8'd1;
+   assign longout = narrow + 8'd1;
-   wire [63:0] quadout = quad + 64'd1;
+   assign quadout = quad + 64'd1;
 `endif
 endmodule

test_regress/t/t_inst_comma.v

@@ -62,5 +62,5 @@ module sub (input [7:0] allbits, input [1:0] onebit, output bitout);
    `INLINE_MODULE
      parameter integer P = 0;
    initial if (P != 1) $stop;
-   wire bitout = (^ onebit) ^ (^ allbits);
+   assign bitout = (^ onebit) ^ (^ allbits);
 endmodule

test_regress/t/t_inst_signed1.v

@@ -40,8 +40,8 @@ endmodule
 //msg2540
 module sub1 (
              input signed  i,
-             output signed o);
+             output wire signed o);
-   wire signed o = ~i;
+   assign o = ~i;
 endmodule
 
 module sub2 (i,o);

test_regress/t/t_inst_tree.v

@@ -65,40 +65,40 @@ module ps (input printclk);
    always @ (posedge printclk) $write("[%0t] %m: Clocked\n", $time);
 endmodule
 
-module l1 (input [7:0] a, output [7:0] z);
+module l1 (input [7:0] a, output [7:0] z `PUBLIC);
    `INLINE_MODULE
    wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC;
-   wire [7:0] z `PUBLIC; assign z = z0+z1;
+   assign z = z0+z1;
    l2 u0 (a, z0);   l2 u1 (a, z1);
 endmodule
 
-module l2 (input [7:0] a, output [7:0] z);
+module l2 (input [7:0] a, output [7:0] z `PUBLIC);
    `INLINE_MODULE
    wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC;
-   wire [7:0] z `PUBLIC; assign z = z0+z1;
+   assign z = z0+z1;
    wire [7:0] a1 = a+8'd1;
    l3 u0 (a, z0);   l3 u1 (a1, z1);
 endmodule
 
-module l3 (input [7:0] a, output [7:0] z);
+module l3 (input [7:0] a, output [7:0] z `PUBLIC);
    `INLINE_MODULE
    wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC;
-   wire [7:0] z `PUBLIC; assign z = z0+z1;
+   assign z = z0+z1;
    wire [7:0] a1 = a+8'd1;
    l4 u0 (a, z0);   l4 u1 (a1, z1);
 endmodule
 
-module l4 (input [7:0] a, output [7:0] z);
+module l4 (input [7:0] a, output [7:0] z `PUBLIC);
    `INLINE_MODULE
    wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC;
-   wire [7:0] z `PUBLIC; assign z = z0+z1;
+   assign z = z0+z1;
    wire [7:0] a1 = a+8'd1;
    l5 #(1) u0 (a, z0);   l5 #(2) u1 (a1, z1);
 endmodule
 
-module l5 (input [7:0] a, output [7:0] z);
+module l5 (input [7:0] a, output [7:0] z `PUBLIC);
    `INLINE_MODULE
    parameter PARAM = 5;
    wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC;
-   wire [7:0] z `PUBLIC; assign z = a;
+   assign z = a;
 endmodule

test_regress/t/t_math_vliw.v

@@ -62,7 +62,7 @@ module vliw (
 	     input[2:0]    szlfpf,
 	     input[15:0]   dzosui,
 	     input[31:0]   zndrba,
-	     output [223:0] bxiouf
+	     output wire [223:0] bxiouf
 	     );
 
    wire [463:0] zhknfc  =   ({29{~apqrli}} & {mglehy, drricx[215:8]})
@@ -71,7 +71,7 @@ module vliw (
 		| ({21{dzosui}}  & zhknfc[335:0]);
    wire [335:0] viuvoc = umntwz << {szlfpf, 4'b0000};
    wire [223:0] rzyeut = viuvoc[335:112];
-   wire [223:0] bxiouf = {rzyeut[7:0],
+   assign bxiouf       = {rzyeut[7:0],
              		  rzyeut[15:8],
              		  rzyeut[23:16],
              		  rzyeut[31:24],

test_regress/t/t_param_wide_io.v

@@ -14,6 +14,6 @@ module t
 	output [P&7 - 1:0] out
 	);
 
-   wire out = in;
+   assign out = in;
 
 endmodule

test_regress/t/t_reloop_cam.v

@@ -112,7 +112,6 @@ module cam
    output logic         rdat_val_d2r
    );
 
-   logic [30:0]         rdat_d2r;
    logic                camen_d1r;
    logic                inval_d1r;
    logic                ren_d1r;
@@ -122,8 +121,6 @@ module cam
    logic [30:0]         wdat_d1r;
    logic                wdat_val_d1r;
 
-   logic [30:0]         wdat;
-
    always_ff @(posedge clk) begin
       camen_d1r <= camen;
       inval_d1r <= inval;

test_regress/t/t_vams_wreal.v

@@ -105,7 +105,7 @@ module within_range
    parameter real V_MAX = 10;
 
    wreal in_int = vpass - gnd;
-   wire out = (V_MIN <= in_int && in_int <= V_MAX);
+   assign out = (V_MIN <= in_int && in_int <= V_MAX);
 endmodule
 
 
@@ -128,9 +128,9 @@ module first_level
    second_level second_level(.in(in), .out(out));
 endmodule
 
-module second_level
+module second_level(in, out);
-  (input in,
+   input in;
-   output out);
+   output out;
    wreal out;
    assign out = in ? 1.23456: 7.8910;
 endmodule