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https://github.com/verilator/verilator.git
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Internals: Refactor input/output to new class in prep for ref support.
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+16
-16
@@ -56,21 +56,21 @@ private:
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nodep->lvalue(true);
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}
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if (nodep->varp()) {
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if (nodep->lvalue() && nodep->varp()->isInOnly()) {
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if (!m_ftaskp) {
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nodep->v3warn(ASSIGNIN,"Assigning to input variable: "<<nodep->prettyName());
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}
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}
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}
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if (nodep->lvalue() && !m_ftaskp
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&& nodep->varp()->isReadOnly()) {
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nodep->v3warn(ASSIGNIN,"Assigning to input/const variable: "
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<<nodep->prettyName());
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}
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}
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iterateChildren(nodep);
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}
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// Nodes that start propagating down lvalues
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virtual void visit(AstPin* nodep) {
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if (nodep->modVarp() && nodep->modVarp()->isOutput()) {
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// When the varref's were created, we didn't know the I/O state
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// Now that we do, and it's from a output, we know it's a lvalue
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m_setRefLvalue = true;
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if (nodep->modVarp() && nodep->modVarp()->isWritable()) {
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// When the varref's were created, we didn't know the I/O state
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// Now that we do, and it's from a output, we know it's a lvalue
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m_setRefLvalue = true;
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iterateChildren(nodep);
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m_setRefLvalue = false;
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} else {
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@@ -238,14 +238,14 @@ private:
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if (!taskp) return;
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for (AstNode* stmtp = taskp->stmtsp(); stmtp && pinp; stmtp=stmtp->nextp()) {
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if (const AstVar* portp = VN_CAST(stmtp, Var)) {
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if (portp->isIO()) {
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if (portp->isInput()) {
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if (portp->isIO()) {
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if (portp->isWritable()) {
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m_setRefLvalue = true;
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iterate(pinp);
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} else { // Output or Inout
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m_setRefLvalue = true;
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m_setRefLvalue = false;
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} else {
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iterate(pinp);
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m_setRefLvalue = false;
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}
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}
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// Advance pin
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pinp = pinp->nextp();
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}
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