mirror of
https://github.com/verilator/verilator.git
synced 2026-10-06 01:54:01 +02:00
Internals: Refactor input/output to new class in prep for ref support.
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+33
-27
@@ -317,23 +317,26 @@ private:
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// Public variable at the lower module end - we need to make sure we propagate
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// the logic changes up and down; if we aliased, we might remove the change detection
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// on the output variable.
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UINFO(9,"public pin assign: "<<exprvarrefp<<endl);
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if (nodep->isInput()) nodep->v3fatalSrc("Outputs only - inputs use AssignAlias");
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m_modp->addStmtp(new AstAssignW(nodep->fileline(),
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new AstVarRef(nodep->fileline(), exprvarrefp->varp(), true),
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new AstVarRef(nodep->fileline(), nodep, false)));
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} else if (nodep->isIfaceRef()) {
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m_modp->addStmtp(new AstAssignVarScope(nodep->fileline(),
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new AstVarRef(nodep->fileline(), nodep, true),
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new AstVarRef(nodep->fileline(), exprvarrefp->varp(), false)));
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AstNode* nodebp=exprvarrefp->varp();
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nodep ->fileline()->modifyStateInherit(nodebp->fileline());
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nodebp->fileline()->modifyStateInherit(nodep ->fileline());
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} else {
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// Do to inlining child's variable now within the same module, so a AstVarRef not AstVarXRef below
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m_modp->addStmtp(new AstAssignAlias(nodep->fileline(),
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new AstVarRef(nodep->fileline(), nodep, true),
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new AstVarRef(nodep->fileline(), exprvarrefp->varp(), false)));
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UINFO(9,"public pin assign: "<<exprvarrefp<<endl);
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if (nodep->isNonOutput()) nodep->v3fatalSrc("Outputs only - inputs use AssignAlias");
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m_modp->addStmtp(
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new AstAssignW(nodep->fileline(),
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new AstVarRef(nodep->fileline(), exprvarrefp->varp(), true),
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new AstVarRef(nodep->fileline(), nodep, false)));
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} else if (nodep->isIfaceRef()) {
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m_modp->addStmtp(
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new AstAssignVarScope(nodep->fileline(),
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new AstVarRef(nodep->fileline(), nodep, true),
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new AstVarRef(nodep->fileline(), exprvarrefp->varp(), false)));
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AstNode* nodebp=exprvarrefp->varp();
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nodep ->fileline()->modifyStateInherit(nodebp->fileline());
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nodebp->fileline()->modifyStateInherit(nodep ->fileline());
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} else {
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// Do to inlining child's variable now within the same module, so a AstVarRef not AstVarXRef below
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m_modp->addStmtp(
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new AstAssignAlias(nodep->fileline(),
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new AstVarRef(nodep->fileline(), nodep, true),
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new AstVarRef(nodep->fileline(), exprvarrefp->varp(), false)));
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AstNode* nodebp=exprvarrefp->varp();
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nodep ->fileline()->modifyStateInherit(nodebp->fileline());
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nodebp->fileline()->modifyStateInherit(nodep ->fileline());
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@@ -549,11 +552,12 @@ private:
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AstNode* connectRefp = pinp->exprp();
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if (!VN_IS(connectRefp, Const) && !VN_IS(connectRefp, VarRef)) {
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pinp->v3fatalSrc("Unknown interconnect type; pinReconnectSimple should have cleared up");
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}
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if (pinNewVarp->isOutOnly() && VN_IS(connectRefp, Const)) {
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pinp->v3error("Output port is connected to a constant pin, electrical short");
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}
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pinp->v3fatalSrc("Unknown interconnect type; pinReconnectSimple should have cleared up");
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}
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if (pinNewVarp->direction() == VDirection::OUTPUT
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&& VN_IS(connectRefp, Const)) {
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pinp->v3error("Output port is connected to a constant pin, electrical short");
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}
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// Propagate any attributes across the interconnect
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pinNewVarp->propagateAttrFrom(pinOldVarp);
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@@ -567,11 +571,13 @@ private:
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UINFO(6,"One-to-one "<<connectRefp<<endl);
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UINFO(6," -to "<<pinNewVarp<<endl);
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pinNewVarp->user2p(connectRefp);
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// Public output inside the cell must go via an assign rather than alias
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// Else the public logic will set the alias, losing the value to be propagated up
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// (InOnly isn't a problem as the AssignAlias will create the assignment for us)
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pinNewVarp->user3(pinNewVarp->isSigUserRWPublic() && pinNewVarp->isOutOnly());
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}
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// Public output inside the cell must go via an assign rather
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// than alias. Else the public logic will set the alias, losing
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// the value to be propagated up (InOnly isn't a problem as the
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// AssignAlias will create the assignment for us)
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pinNewVarp->user3(pinNewVarp->isSigUserRWPublic()
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&& pinNewVarp->direction()==VDirection::OUTPUT);
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}
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// Cleanup var names, etc, to not conflict
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{ InlineRelinkVisitor(newmodp, m_modp, nodep); }
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// Move statements to top module
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