Tests: Untabify some tests.

2024-09-01 21:12:37 -04:00 · 2024-09-01 21:12:37 -04:00 · b698bfd850
parent c9970ff822
commit b698bfd850
15 changed files with 275 additions and 280 deletions
--- a/test_regress/t/t_type_match.v
+++ b/test_regress/t/t_type_match.v
@ -1,10 +1,5 @@
 // DESCRIPTION: Verilator: Verilog Test module
 //
-// This module takes a single clock input, and should either
-//      $write("*-* All Finished *-*\n");
-//      $finish;
-// on success, or $stop.
-//
 // issue #5125
 // type used for __Vtrigprevexpr signal do not match type used for i/o port
 //