luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Move some unsupported syntax to parser for cleaner errors.

This commit is contained in:
Wilson Snyder 2018-10-11 21:57:07 -04:00
parent 6047049fc7
commit b59c23d346
2 changed files with 9 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/verilog.l
View File

@ -493,6 +493,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
"pure" { FL; return yPURE; } "pure" { FL; return yPURE; }
"rand" { FL; return yRAND; } "rand" { FL; return yRAND; }
"randc" { FL; return yRANDC; } "randc" { FL; return yRANDC; }
"ref" { FL; return yREF; }
"restrict" { FL; return yRESTRICT; } "restrict" { FL; return yRESTRICT; }
"return" { FL; return yRETURN; } "return" { FL; return yRETURN; }
"shortint" { FL; return ySHORTINT; } "shortint" { FL; return ySHORTINT; }
@ -540,7 +541,6 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
"randcase" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "randcase" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
"randomize" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "randomize" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
"randsequence" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "randsequence" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
"ref" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
"sequence" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "sequence" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
"solve" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "solve" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
"super" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "super" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); }
@ -1067,8 +1067,8 @@ void V3ParseImp::lexToken() {
yylval = curValue; yylval = curValue;
// Now potentially munge the current token // Now potentially munge the current token
if (token == yCONST__LEX) { if (token == yCONST__LEX) {
//UNSUP if (nexttok == yREF) token = yCONST__REF; if (nexttok == yREF) token = yCONST__REF;
token = yCONST__ETC; else token = yCONST__ETC;
} }
else if (token == yGLOBAL__LEX) { else if (token == yGLOBAL__LEX) {
if (nexttok == yCLOCKING) token = yGLOBAL__CLOCKING; if (nexttok == yCLOCKING) token = yGLOBAL__CLOCKING;

10
src/verilog.y
View File

@ -320,6 +320,7 @@ class AstSenTree;
%token<fl> yCLOCKING "clocking" %token<fl> yCLOCKING "clocking"
%token<fl> yCONST__ETC "const" %token<fl> yCONST__ETC "const"
%token<fl> yCONST__LEX "const-in-lex" %token<fl> yCONST__LEX "const-in-lex"
%token<fl> yCONST__REF "const-then-ref"
%token<fl> yCMOS "cmos" %token<fl> yCMOS "cmos"
%token<fl> yCONTEXT "context" %token<fl> yCONTEXT "context"
%token<fl> yCONTINUE "continue" %token<fl> yCONTINUE "continue"
@ -399,6 +400,7 @@ class AstSenTree;
%token<fl> yRCMOS "rcmos" %token<fl> yRCMOS "rcmos"
%token<fl> yREAL "real" %token<fl> yREAL "real"
%token<fl> yREALTIME "realtime" %token<fl> yREALTIME "realtime"
%token<fl> yREF "ref"
%token<fl> yREG "reg" %token<fl> yREG "reg"
%token<fl> yREPEAT "repeat" %token<fl> yREPEAT "repeat"
%token<fl> yRESTRICT "restrict" %token<fl> yRESTRICT "restrict"
@ -1301,8 +1303,8 @@ port_direction: // ==IEEE: port_direction + tf_port_direction
yINPUT { VARIO(INPUT); } yINPUT { VARIO(INPUT); }
| yOUTPUT { VARIO(OUTPUT); } | yOUTPUT { VARIO(OUTPUT); }
| yINOUT { VARIO(INOUT); } | yINOUT { VARIO(INOUT); }
//UNSUP yREF { VARIO(REF); } | yREF { $<fl>1->v3error("Unsupported: ref port"); VARIO(INOUT); }
//UNSUP yCONST__REF yREF { VARIO(CONSTREF); } | yCONST__REF yREF { $<fl>1->v3error("Unsupported: const ref port"); VARIO(INOUT); }
; ;
port_directionReset: // IEEE: port_direction that starts a port_declaraiton port_directionReset: // IEEE: port_direction that starts a port_declaraiton
@ -1310,8 +1312,8 @@ port_directionReset: // IEEE: port_direction that starts a port_declaraiton
yINPUT { VARRESET_NONLIST(UNKNOWN); VARIO(INPUT); } yINPUT { VARRESET_NONLIST(UNKNOWN); VARIO(INPUT); }
| yOUTPUT { VARRESET_NONLIST(UNKNOWN); VARIO(OUTPUT); } | yOUTPUT { VARRESET_NONLIST(UNKNOWN); VARIO(OUTPUT); }
| yINOUT { VARRESET_NONLIST(UNKNOWN); VARIO(INOUT); } | yINOUT { VARRESET_NONLIST(UNKNOWN); VARIO(INOUT); }
//UNSUP yREF { VARRESET_NONLIST(UNKNOWN); VARIO(REF); } | yREF { $<fl>1->v3error("Unsupported: ref port"); VARRESET_NONLIST(UNKNOWN); VARIO(INOUT); }
//UNSUP yCONST__REF yREF { VARRESET_NONLIST(UNKNOWN); VARIO(CONSTREF); } | yCONST__REF yREF { $<fl>1->v3error("Unsupported: const ref port"); VARRESET_NONLIST(UNKNOWN); VARIO(INOUT); }
; ;
port_declaration<nodep>: // ==IEEE: port_declaration port_declaration<nodep>: // ==IEEE: port_declaration