Fix enum items under packages.
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4968a2abc5
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@ -103,6 +103,7 @@ public:
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if (!diddump && v3Global.opt.dumpTree()) {
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diddump = true;
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m_syms.dumpFilePrefixed("linkdot-preerr");
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v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("linkdot-preerr.tree"));
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}
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}
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@ -1445,6 +1446,10 @@ private:
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}
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}
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}
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virtual void visit(AstEnumItemRef* nodep, AstNUser*) {
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// EnumItemRef may be under a dot. Should already be resolved.
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nodep->iterateChildren(*this);
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}
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virtual void visit(AstVar* nodep, AstNUser*) {
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checkNoDot(nodep);
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nodep->iterateChildren(*this);
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@ -0,0 +1,18 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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);
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execute (
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check_finished=>1,
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);
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ok(1);
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1;
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@ -0,0 +1,30 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2013 by Wilson Snyder.
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package pkg;
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typedef enum bit [1:0]
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{
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E__NOT = 2'b00,
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E__VAL = 2'b11
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} E_t;
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endpackage
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module t;
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reg [1:0] ttype;
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reg m;
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initial begin
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ttype = pkg::E__NOT;
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m = (ttype == pkg::E__VAL);
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if (m != 1'b0) $stop;
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ttype = pkg::E__VAL;
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m = (ttype == pkg::E__VAL);
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if (m != 1'b1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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