Tests: Move t_math_synmul to extended tests.
This commit is contained in:
Wilson Snyder
parent
defd05bdd7
commit
b3eab9d78a
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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scenarios(simulator => 1);
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top_filename("t/t_math_synmul.v");
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$Self->{cycles} = $Self->{benchmark}||0;
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$Self->{cycles} = 100 if $Self->{cycles}<100;
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$Self->{sim_time} = $Self->{cycles}*100;
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compile(
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v_flags2 => ["+define+SIM_CYCLES=$Self->{cycles}",
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"--stats",
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"-Wno-UNOPTTHREADS"],
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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scenarios(simulator => 1);
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compile(
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verilator_flags2 => ["-Wno-UNOPTTHREADS"],
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2008 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg negate;
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reg enable;
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wire [31:0] datA = crc[31:0];
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wire [31:0] datB = crc[63:32];
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// Predict result
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wire [63:0] muled = (negate ? (- {32'h0,datA} * {32'h0,datB})
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: ( {32'h0,datA} * {32'h0,datB}));
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reg [63:0] muled_d1;
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reg [63:0] muled_d2;
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reg [63:0] muled_d3;
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reg [63:0] muled_d4;
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reg enable_d1;
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reg enable_d2;
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reg enable_d3;
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always @ (posedge clk) enable_d1 <= enable;
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always @ (posedge clk) enable_d2 <= enable_d1;
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always @ (posedge clk) enable_d3 <= enable_d2;
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always @ (posedge clk) if (enable) muled_d1 <= muled;
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always @ (posedge clk) if (enable_d1) muled_d2 <= muled_d1;
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always @ (posedge clk) if (enable_d2) muled_d3 <= muled_d2;
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always @ (posedge clk) if (enable_d3) muled_d4 <= muled_d3;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [64:0] product_d4; // From test of t_math_synmul_mul.v
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// End of automatics
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t_math_synmul_mul test (/*AUTOINST*/
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// Outputs
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.product_d4 (product_d4[64:0]),
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// Inputs
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.clk (clk),
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.enable (enable),
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.negate (negate),
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.datA (datA[31:0]),
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.datB (datB[31:0]));
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integer cycs_enabled; initial cycs_enabled = 0;
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x e=%x n=%x a*b=%x synmul=%x\n",$time, cyc,
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crc, enable, negate, muled_d4, product_d4[63:0]);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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negate <= 1'b0; // Negation not currently supported
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// Always enable in low cycle counts to clear out the pipe
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//enable <= 1'b1; // 100% activity factor
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enable <= (cyc<10 || cyc[4]); // 50% activity factor
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//enable <= (cyc<10 || cyc[4]&cyc[3]); // 25% activity factor
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if (enable) cycs_enabled=cycs_enabled+1;
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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end
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else if (cyc<10) begin
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end
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else begin
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if (product_d4[63:0] !== muled_d4) begin
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$write("[%0t] BAD product, got=%x exp=%x at cyc 0x%x\n",$time, product_d4[63:0], muled_d4, cyc);
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$stop;
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end
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if (cyc==99) begin
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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end
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`ifndef SIM_CYCLES
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`define SIM_CYCLES 99
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`endif
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if (cyc==`SIM_CYCLES) begin
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$write("- Cycles=%0d, Activity factor=%0d%%\n", cyc, ((cycs_enabled*100)/cyc));
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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