Add error on string addition

This commit is contained in:
Wilson Snyder 2025-09-20 13:47:17 -04:00
parent e0e8503151
commit b237eec801
4 changed files with 60 additions and 0 deletions

View File

@ -7307,6 +7307,18 @@ class WidthVisitor final : public VNVisitor {
iterateCheckReal(nodep, "LHS", nodep->lhsp(), FINAL); iterateCheckReal(nodep, "LHS", nodep->lhsp(), FINAL);
iterateCheckReal(nodep, "RHS", nodep->rhsp(), FINAL); iterateCheckReal(nodep, "RHS", nodep->rhsp(), FINAL);
return; return;
} else if (nodep->lhsp()->isString() || nodep->rhsp()->isString()) {
nodep->v3error(
"Operator "
<< nodep->prettyTypeName()
<< " is not legal on string data types (IEEE 1800-2023 6.16)\n"
<< (VN_IS(nodep, Add)
? (nodep->warnMore()
+ "... Suggest to concatenate strings use '{LHS, RHS, ...}'")
: ""));
nodep->replaceWith(new AstConst{nodep->fileline(), AstConst::String{}, ""});
VL_DO_DANGLING(pushDeletep(nodep), nodep);
return;
} else { } else {
const int width = std::max(nodep->lhsp()->width(), nodep->rhsp()->width()); const int width = std::max(nodep->lhsp()->width(), nodep->rhsp()->width());
const int mwidth = std::max(nodep->lhsp()->widthMin(), nodep->rhsp()->widthMin()); const int mwidth = std::max(nodep->lhsp()->widthMin(), nodep->rhsp()->widthMin());

View File

@ -0,0 +1,12 @@
%Error: t/t_string_add_bad.v:13:9: Operator ADD is not legal on string data types (IEEE 1800-2023 6.16)
: ... note: In instance 't'
: ... Suggest to concatenate strings use '{LHS, RHS, ...}'
13 | s += $sformatf(" a%0d", a);
| ^~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_string_add_bad.v:14:13: Operator ADD is not legal on string data types (IEEE 1800-2023 6.16)
: ... note: In instance 't'
: ... Suggest to concatenate strings use '{LHS, RHS, ...}'
14 | s = s + s;
| ^
%Error: Exiting due to

View File

@ -0,0 +1,16 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('linter')
test.lint(fails=True, expect_filename=test.golden_filename)
test.passes()

View File

@ -0,0 +1,20 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t;
string s;
initial begin
for (int a = 0; a < 3; ++a) begin : a_loop
s += $sformatf(" a%0d", a); // <--- Error: += is not legal on strings
s = s + s; // <--- Error: += is not legal on strings
end
$stop;
end
endmodule