Verilog format

This commit is contained in:
Veripool API Bot
2026-02-12 18:23:56 -05:00
committed by Wilson Snyder
parent 13b1321985
commit b0fdbff6eb
33 changed files with 362 additions and 290 deletions
+4 -4
View File
@@ -8,16 +8,16 @@ interface simple_bad_if;
logic [7:0] value;
endinterface
module t (/*AUTOARG*/
// Inputs
clk
module t ( /*AUTOARG*/
// Inputs
clk
);
input clk;
localparam N = 4;
simple_bad_if ifaces [N-1:0] ();
simple_bad_if ifaces[N-1:0] ();
// BAD: Loop with runtime-variable bound - not unrollable, so the
// interface array index cannot be resolved to a constant.