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Verilog format
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committed by
Wilson Snyder
parent
13b1321985
commit
b0fdbff6eb
@@ -8,16 +8,16 @@ interface simple_bad_if;
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logic [7:0] value;
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endinterface
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module t (/*AUTOARG*/
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// Inputs
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clk
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module t ( /*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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localparam N = 4;
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simple_bad_if ifaces [N-1:0] ();
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simple_bad_if ifaces[N-1:0] ();
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// BAD: Loop with runtime-variable bound - not unrollable, so the
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// interface array index cannot be resolved to a constant.
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