Fix certain generate-if cells causing clone error.

Changes

@@ -14,6 +14,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Minor performance improvements of Verilator compiler runtime.
 
+**** Fix certain generate-if cells causing "clone" error. [Stephane Laurent]
+
 **** Fix line coverage of public functions.  [Soon Koh]
 
 **** Fix SystemC 2.2 deprecated warnings about sensitive() and sc_start().

bin/verilator

@@ -2378,21 +2378,29 @@ faster than many popular commercial simulators.
 Many people have provided ideas and other assistance with Verilator.
 
 The major corporate sponsors of Verilator, by providing funds or equipment
-grants, are Compaq Corporation, Digital Equipment Corporation, Maker
-Communications, Sun Microsystems, Nauticus Networks, and SiCortex.
+grants include Compaq Corporation, Digital Equipment Corporation, Intel
+Corporation, Maker Communications, MicroTune Inc., Sun Microsystems,
+Nauticus Networks, and SiCortex Inc.
 
-The people who have contributed code or other major functionality are Paul
-Wasson, Duane Galbi, and Wilson Snyder.  Major testers include Jeff Dutton,
-Ralf Karge, David Hewson, Wim Michiels, and Gene Weber.
+The people who have contributed code or other major functionality are Lane
+Brooks, Duane Galbi, Paul Wasson, and Wilson Snyder.  Major testers include
+Jeff Dutton, Ralf Karge, David Hewson, Wim Michiels, and Gene Weber.
 
 Some of the people who have provided ideas and feedback for Verilator
-include Hans Van Antwerpen, Jens Arm, David Black, Gregg Bouchard, Chris
-Boumenot, John Brownlee, Lauren Carlson, Robert A. Clark, John Deroo, Danny
-Ding, Jeff Dutton, Eugen Fekete, Sam Gladstone, Thomas Hawkins, Mike Kagen,
-Ralf Karge, Dan Katz, Sol Katzman, Gernot Koch, Steve Kolecki, Steve Lang,
-Charlie Lind, Dan Lussier, Fred Ma, Wim Michiels, John Murphy, Richard
-Myers, Paul Nitza, Lisa Noack, Renga Sundararajan, Shawn Wang, Greg Waters,
-Eugene Weber, Leon Wildman, and Mat Zeno.
+include David Addison, Hans Van Antwerpen, Vasu Arasanipalai, Jens Arm,
+Jeremy Bennett, David Black, Gregg Bouchard, Chris Boumenot, Bryan Brady,
+Lane Brooks, John Brownlee, Lauren Carlson, Robert A. Clark, Allan
+Cochrane, Gunter Dannoritzer, Bernard Deadman, John Deroo, John Dickol,
+Danny Ding, Jeff Dutton, Robert Farrell, Eugen Fekete, Sam Gladstone,
+Thomas Hawkins, David Hewson, Jae Hossell, Ben Jackson, Mike Kagen,
+Patricio Kaplan, Ralf Karge, Dan Katz, Sol Katzman, Jonathan Kimmitt,
+Gernot Koch, Steve Kolecki, Steve Lang, Stephane Laurent, Charlie Lind, Dan
+Lussier, Fred Ma, Wim Michiels, John Murphy, Richard Myers, Paul Nitza,
+Lisa Noack, Mark Nodine, Niranjan Prabhu, Oleg Rodionov, Mike Shinkarovsky,
+Rafael Shirakawa, Rodney Sinclair, John Stroebel, Emerson Suguimoto, Renga
+Sundararajan, Stefan Thiede, Steve Tong, Holger Waechtler, Shawn Wang, Greg
+Waters, Eugene Weber, Leon Wildman, Gerald Williams, Johan Wouters, and
+Ding Xiaoliang.
 
 =head1 DISTRIBUTION
 

src/V3Inline.cpp

@@ -305,7 +305,7 @@ private:
     virtual void visit(AstModule* nodep, AstNUser*) {
 	m_stmtCnt = 0;
 	m_modp = nodep;
-	m_modp->user2(true);
+	m_modp->user2(true);  // Allowed = true
 	if (m_modp->modPublic()) cantInline("modPublic");
 	//
 	nodep->iterateChildren(*this);

src/V3LinkLevel.cpp

@@ -60,7 +60,8 @@ private:
 	m_modp = holdmodp;
     }
     // For speed, don't recurse things that can't have cells
-    virtual void visit(AstNodeStmt*, AstNUser*) {}
+    // Must do statements to support Generates, math though...
+    virtual void visit(AstNodeMath* nodep, AstNUser*) {}
     virtual void visit(AstNode* nodep, AstNUser*) {
 	// Default: Just iterate
 	nodep->iterateChildren(*this);

test_regress/t/t_gen_mislevel.pl

@@ -0,0 +1,17 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_gen_mislevel.v

@@ -0,0 +1,43 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2008 by Wilson Snyder.
+
+/// We define the modules in "backward" order.
+
+module d;
+endmodule
+
+module b;
+   generate if (1) begin
+      c c1 ();
+      c c2 ();
+   end
+   endgenerate
+endmodule
+
+module c;
+   generate if (1) begin
+      d d1 ();
+      d d2 ();
+   end
+   endgenerate
+endmodule
+
+module a;
+   generate if (1) begin
+      b b1 ();
+      b b2 ();
+   end
+   endgenerate
+endmodule
+
+module t (/*AUTOARG*/);
+
+   a a1 ();
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule