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Add interface port visibility in traces, bug1594.

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This commit is contained in:
Todd Strader
2019-11-08 08:26:48 -05:00
parent 2eda38c4d1
commit abe95f3ab3
7 changed files with 443 additions and 6 deletions
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+2
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@@ -20,6 +20,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
*** Suppress 'command failed' on normal errors. *** Suppress 'command failed' on normal errors.
*** Add interface port visibility in traces, bug1594. [Todd Strader]
**** Increase case duplicate/incomplete to 16 bit tables, bug1545. [Yossi Nivin] **** Increase case duplicate/incomplete to 16 bit tables, bug1545. [Yossi Nivin]
**** Support quoted arguments in -f files, bug1535. [Yves Mathieu] **** Support quoted arguments in -f files, bug1535. [Yves Mathieu]
src/V3TraceDecl.cpp
+25 -2
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@@ -52,6 +52,7 @@ private:
AstVarScope* m_traVscp; // Signal being trace constructed AstVarScope* m_traVscp; // Signal being trace constructed
AstNode* m_traValuep; // Signal being traced's value to trace in it AstNode* m_traValuep; // Signal being traced's value to trace in it
string m_traShowname; // Signal being traced's component name string m_traShowname; // Signal being traced's component name
string m_ifShowname; // Interface reference being traced's scope name
VDouble0 m_statSigs; // Statistic tracking VDouble0 m_statSigs; // Statistic tracking
VDouble0 m_statIgnSigs; // Statistic tracking VDouble0 m_statIgnSigs; // Statistic tracking
@@ -160,8 +161,12 @@ private:
// Compute show name // Compute show name
// This code assumes SPTRACEVCDC_VERSION >= 1330; // This code assumes SPTRACEVCDC_VERSION >= 1330;
// it uses spaces to separate hierarchy components. // it uses spaces to separate hierarchy components.
m_traShowname = AstNode::vcdName(scopep->name() + " " + varp->name()); if (m_ifShowname.empty()) {
if (m_traShowname.substr(0, 4) == "TOP ") m_traShowname.replace(0, 4, ""); m_traShowname = AstNode::vcdName(scopep->name() + " " + varp->name());
if (m_traShowname.substr(0, 4) == "TOP ") m_traShowname.replace(0, 4, "");
} else {
m_traShowname = AstNode::vcdName(m_ifShowname + " " + varp->name());
}
UASSERT_OBJ(m_initSubFuncp, nodep, "NULL"); UASSERT_OBJ(m_initSubFuncp, nodep, "NULL");
m_traVscp = nodep; m_traVscp = nodep;
@@ -195,6 +200,24 @@ private:
iterate(nodep->subDTypep()->skipRefp()); iterate(nodep->subDTypep()->skipRefp());
} }
} }
virtual void visit(AstIfaceRefDType* nodep) {
if (m_traVscp && nodep->ifacep()) {
// Stash the signal state because we're going to go through another VARSCOPE
AstVarScope* traVscp = m_traVscp;
AstNode* traValuep = m_traValuep;
{
m_traVscp = NULL;
m_traValuep = NULL;
m_ifShowname = m_traShowname;
m_traShowname = "";
iterate(nodep->ifacep());
m_traShowname = m_ifShowname;
m_ifShowname = "";
}
m_traVscp = traVscp;
m_traValuep = traValuep;
}
}
virtual void visit(AstUnpackArrayDType* nodep) { virtual void visit(AstUnpackArrayDType* nodep) {
// Note more specific dtypes above // Note more specific dtypes above
if (m_traVscp) { if (m_traVscp) {
test_regress/t/t_interface1_modport.v
+18 -4
View File
@@ -22,20 +22,34 @@ module t (/*AUTOARG*/
ifc itop(); ifc itop();
sub c1 (.isub(itop), sub c1 (.isub(itop),
.i_value(4)); .i_value(cyc));
sub2 c2 (.isub2(itop),
.i_value(cyc));
always @(*) itop.hidden_from_isub = cyc + 1;
always @ (posedge clk) begin always @ (posedge clk) begin
cyc <= cyc + 1; cyc <= cyc + 1;
if (cyc==20) begin if (cyc==20) begin
if (itop.value != 4) $stop; if (itop.value != 20) $stop;
itop.hidden_from_isub = 20; if (itop.hidden_from_isub != 21) $stop;
if (itop.hidden_from_isub != 20) $stop;
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end
end end
endmodule endmodule
module sub2
(
ifc.out_modport isub2,
input integer i_value
);
sub c3 (.isub(isub2),
.i_value(i_value));
endmodule
module sub module sub
`ifdef NANSI // bug868 `ifdef NANSI // bug868
( (
test_regress/t/t_interface1_modport_trace.out
+183
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@@ -0,0 +1,183 @@
$version Generated by VerilatedVcd $end
$date Thu Nov 7 18:07:03 2019
$end
$timescale 1ns $end
$scope module top $end
$var wire 1 & clk $end
$scope module t $end
$var wire 1 & clk $end
$var wire 32 # cyc [31:0] $end
$scope module c1 $end
$var wire 32 # i_value [31:0] $end
$scope module isub $end
$var wire 32 $ hidden_from_isub [31:0] $end
$var wire 32 % value [31:0] $end
$upscope $end
$upscope $end
$scope module c2 $end
$var wire 32 # i_value [31:0] $end
$scope module c3 $end
$var wire 32 # i_value [31:0] $end
$scope module isub $end
$var wire 32 $ hidden_from_isub [31:0] $end
$var wire 32 % value [31:0] $end
$upscope $end
$upscope $end
$scope module isub2 $end
$var wire 32 $ hidden_from_isub [31:0] $end
$var wire 32 % value [31:0] $end
$upscope $end
$upscope $end
$scope module itop $end
$var wire 32 $ hidden_from_isub [31:0] $end
$var wire 32 % value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
b00000000000000000000000000000001 #
b00000000000000000000000000000010 $
b00000000000000000000000000000001 %
0&
#10
b00000000000000000000000000000010 #
b00000000000000000000000000000011 $
b00000000000000000000000000000010 %
1&
#15
0&
#20
b00000000000000000000000000000011 #
b00000000000000000000000000000100 $
b00000000000000000000000000000011 %
1&
#25
0&
#30
b00000000000000000000000000000100 #
b00000000000000000000000000000101 $
b00000000000000000000000000000100 %
1&
#35
0&
#40
b00000000000000000000000000000101 #
b00000000000000000000000000000110 $
b00000000000000000000000000000101 %
1&
#45
0&
#50
b00000000000000000000000000000110 #
b00000000000000000000000000000111 $
b00000000000000000000000000000110 %
1&
#55
0&
#60
b00000000000000000000000000000111 #
b00000000000000000000000000001000 $
b00000000000000000000000000000111 %
1&
#65
0&
#70
b00000000000000000000000000001000 #
b00000000000000000000000000001001 $
b00000000000000000000000000001000 %
1&
#75
0&
#80
b00000000000000000000000000001001 #
b00000000000000000000000000001010 $
b00000000000000000000000000001001 %
1&
#85
0&
#90
b00000000000000000000000000001010 #
b00000000000000000000000000001011 $
b00000000000000000000000000001010 %
1&
#95
0&
#100
b00000000000000000000000000001011 #
b00000000000000000000000000001100 $
b00000000000000000000000000001011 %
1&
#105
0&
#110
b00000000000000000000000000001100 #
b00000000000000000000000000001101 $
b00000000000000000000000000001100 %
1&
#115
0&
#120
b00000000000000000000000000001101 #
b00000000000000000000000000001110 $
b00000000000000000000000000001101 %
1&
#125
0&
#130
b00000000000000000000000000001110 #
b00000000000000000000000000001111 $
b00000000000000000000000000001110 %
1&
#135
0&
#140
b00000000000000000000000000001111 #
b00000000000000000000000000010000 $
b00000000000000000000000000001111 %
1&
#145
0&
#150
b00000000000000000000000000010000 #
b00000000000000000000000000010001 $
b00000000000000000000000000010000 %
1&
#155
0&
#160
b00000000000000000000000000010001 #
b00000000000000000000000000010010 $
b00000000000000000000000000010001 %
1&
#165
0&
#170
b00000000000000000000000000010010 #
b00000000000000000000000000010011 $
b00000000000000000000000000010010 %
1&
#175
0&
#180
b00000000000000000000000000010011 #
b00000000000000000000000000010100 $
b00000000000000000000000000010011 %
1&
#185
0&
#190
b00000000000000000000000000010100 #
b00000000000000000000000000010101 $
b00000000000000000000000000010100 %
1&
#195
0&
#200
b00000000000000000000000000010101 #
b00000000000000000000000000010110 $
b00000000000000000000000000010101 %
1&
test_regress/t/t_interface1_modport_trace.pl
+3
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@@ -19,5 +19,8 @@ execute(
check_finished => 1, check_finished => 1,
); );
vcd_identical($Self->trace_filename,
$Self->{golden_filename});
ok(1); ok(1);
1; 1;
test_regress/t/t_interface1_modport_trace_fst.out
+186
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@@ -0,0 +1,186 @@
$date
Fri Nov 8 06:41:16 2019
$end
$version
fstWriter
$end
$timescale
1ns
$end
$scope module top $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var integer 32 " cyc $end
$scope module c1 $end
$scope module isub $end
$var integer 32 # hidden_from_isub $end
$var integer 32 $ value $end
$upscope $end
$var wire 32 " i_value $end
$upscope $end
$scope module c2 $end
$scope module isub2 $end
$var integer 32 # hidden_from_isub $end
$var integer 32 $ value $end
$upscope $end
$var wire 32 " i_value $end
$scope module c3 $end
$scope module isub $end
$var integer 32 # hidden_from_isub $end
$var integer 32 $ value $end
$upscope $end
$var wire 32 " i_value $end
$upscope $end
$upscope $end
$scope module itop $end
$var integer 32 # hidden_from_isub $end
$var integer 32 $ value $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
0!
b00000000000000000000000000000001 "
b00000000000000000000000000000010 #
b00000000000000000000000000000001 $
#10
b00000000000000000000000000000010 $
b00000000000000000000000000000011 #
b00000000000000000000000000000010 "
1!
#15
0!
#20
1!
b00000000000000000000000000000011 "
b00000000000000000000000000000100 #
b00000000000000000000000000000011 $
#25
0!
#30
1!
b00000000000000000000000000000100 $
b00000000000000000000000000000101 #
b00000000000000000000000000000100 "
#35
0!
#40
1!
b00000000000000000000000000000101 "
b00000000000000000000000000000110 #
b00000000000000000000000000000101 $
#45
0!
#50
1!
b00000000000000000000000000000110 $
b00000000000000000000000000000111 #
b00000000000000000000000000000110 "
#55
0!
#60
1!
b00000000000000000000000000000111 "
b00000000000000000000000000001000 #
b00000000000000000000000000000111 $
#65
0!
#70
1!
b00000000000000000000000000001000 $
b00000000000000000000000000001001 #
b00000000000000000000000000001000 "
#75
0!
#80
1!
b00000000000000000000000000001001 "
b00000000000000000000000000001010 #
b00000000000000000000000000001001 $
#85
0!
#90
1!
b00000000000000000000000000001010 $
b00000000000000000000000000001011 #
b00000000000000000000000000001010 "
#95
0!
#100
1!
b00000000000000000000000000001011 "
b00000000000000000000000000001100 #
b00000000000000000000000000001011 $
#105
0!
#110
1!
b00000000000000000000000000001100 $
b00000000000000000000000000001101 #
b00000000000000000000000000001100 "
#115
0!
#120
1!
b00000000000000000000000000001101 "
b00000000000000000000000000001110 #
b00000000000000000000000000001101 $
#125
0!
#130
1!
b00000000000000000000000000001110 $
b00000000000000000000000000001111 #
b00000000000000000000000000001110 "
#135
0!
#140
1!
b00000000000000000000000000001111 "
b00000000000000000000000000010000 #
b00000000000000000000000000001111 $
#145
0!
#150
1!
b00000000000000000000000000010000 $
b00000000000000000000000000010001 #
b00000000000000000000000000010000 "
#155
0!
#160
1!
b00000000000000000000000000010001 "
b00000000000000000000000000010010 #
b00000000000000000000000000010001 $
#165
0!
#170
1!
b00000000000000000000000000010010 $
b00000000000000000000000000010011 #
b00000000000000000000000000010010 "
#175
0!
#180
1!
b00000000000000000000000000010011 "
b00000000000000000000000000010100 #
b00000000000000000000000000010011 $
#185
0!
#190
1!
b00000000000000000000000000010100 $
b00000000000000000000000000010101 #
b00000000000000000000000000010100 "
#195
0!
#200
1!
b00000000000000000000000000010101 "
b00000000000000000000000000010110 #
b00000000000000000000000000010101 $
test_regress/t/t_interface1_modport_trace_fst.pl
Executable
+26
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@@ -0,0 +1,26 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
scenarios(simulator => 1);
top_filename("t/t_interface1_modport.v");
compile(
verilator_flags2 => ['--trace-fst'],
);
execute(
check_finished => 1,
);
fst2vcd($Self->trace_filename, "$Self->{obj_dir}/simx-fst2vcd.vcd");
vcd_identical("$Self->{obj_dir}/simx-fst2vcd.vcd", $Self->{golden_filename});
ok(1);
1;