Tests: Unsupported test for bug1622.

Signed-off-by: Wilson Snyder <wsnyder@wsnyder.org>

test_regress/t/t_interface_modport_dir_bad.out

@@ -0,0 +1,12 @@
+#Expecting something along the line of:
+
+    %Error: t/t_interface_modport_dir_bad.v:36: Attempt to drive input-only modport: 'data'
+    : ... In instance t.source_i.source_i
+    ctrl.data <= ~ctrl.data;
+    ^~~~
+    %Error: Exiting due to 1 error(s)
+    %Error: t/t_interface_modport_dir_bad.v:37: Attempt to drive input-only modport: 'valid'
+    : ... In instance t.source_i.source_i
+    ctrl.valid<= ~ctrl.valid;
+    ^~~~
+    %Error: Exiting due to 1 error(s)

test_regress/t/t_interface_modport_dir_bad.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt_all} and unsupported("Verilator unsupported, bug1622");
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_interface_modport_dir_bad.v

@@ -0,0 +1,74 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Driss Hafdi
+
+interface validData
+  (
+   input wire clk,
+   input wire rst
+   );
+
+   logic      data;
+   logic      valid;
+
+   modport sink
+     (
+      input data, valid, clk, rst
+      );
+
+   modport source
+     (
+      input  clk, rst,
+      output data, valid
+      );
+endinterface
+
+module sinkMod
+  (
+   validData.sink ctrl,
+   output logic valid_data
+   );
+   always_ff @(posedge ctrl.clk) begin
+      if (ctrl.valid) valid_data <= ctrl.data;
+   end
+endmodule
+
+module sourceMod
+  (
+   validData.source ctrl
+   );
+   always_ff @(posedge ctrl.clk) begin
+      ctrl.data <= ~ctrl.data;
+      ctrl.valid <= ~ctrl.valid;
+   end
+endmodule
+
+module parentSourceMod
+  (
+   validData.sink ctrl
+   );
+   sourceMod source_i (.ctrl);
+endmodule
+
+
+module t (/*AUTOARG*/
+   // Outputs
+   data,
+   // Inputs
+   clk, rst
+   );
+   input clk;
+   input rst;
+   output logic data;
+
+   validData ctrl(.clk, .rst);
+   sinkMod sink_i (.ctrl, .valid_data(data));
+   parentSourceMod source_i (.ctrl);
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule