Report PORTSHORT errors on concat constants, bug 1400.

Changes

@@ -6,6 +6,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ***   Add +verilator+seed, bug1396. [Stan Sokorac]
 
+****  Report PORTSHORT errors on concat constants, bug 1400. [Will Korteland]
+
 ****  Fix VERILATOR_GDB being ignored, msg2860. [Yu Sheng Lin]
 
 ****  Fix $value$plus$args missing verilated_heavy.h. [Yi-Chung Chen]

src/V3Error.h

@@ -50,6 +50,7 @@ public:
 	// Error codes:
 	E_DETECTARRAY,	// Error: Unsupported: Can't detect changes on arrayed variable
         E_MULTITOP,     // Error: Multiple top level modules
+        E_PORTSHORT,    // Error: Output port is connected to a constant, electrical short
         E_TASKNSVAR,    // Error: Task I/O not simple
 	//
 	// Warning codes:
@@ -129,7 +130,7 @@ public:
 	    // Boolean
 	    " I_COVERAGE", " I_TRACING", " I_LINT", " I_DEF_NETTYPE_WIRE",
             // Errors
-	    "DETECTARRAY", "MULTITOP", "TASKNSVAR",
+            "DETECTARRAY", "MULTITOP", "PORTSHORT", "TASKNSVAR",
             // Warnings
 	    " EC_FIRST_WARN",
 	    "ALWCOMBORDER", "ASSIGNDLY", "ASSIGNIN",

src/V3Inline.cpp

@@ -554,10 +554,7 @@ private:
                 if (!VN_IS(connectRefp, Const) && !VN_IS(connectRefp, VarRef)) {
                     pinp->v3fatalSrc("Unknown interconnect type; pinReconnectSimple should have cleared up");
                 }
-                if (pinNewVarp->direction() == VDirection::OUTPUT
+                V3Inst::checkOutputShort(pinp);
-                    && VN_IS(connectRefp, Const)) {
-                    pinp->v3error("Output port is connected to a constant pin, electrical short");
-                }
 
 		// Propagate any attributes across the interconnect
 		pinNewVarp->propagateAttrFrom(pinOldVarp);

src/V3Inst.cpp

@@ -68,10 +68,7 @@ private:
         UINFO(4,"   PIN  "<<nodep<<endl);
         if (!nodep->exprp()) return;  // No-connect
         if (debug()>=9) nodep->dumpTree(cout,"  Pin_oldb: ");
-        if (nodep->modVarp()->direction() == VDirection::OUTPUT
+        V3Inst::checkOutputShort(nodep);
-            && VN_IS(nodep->exprp(), Const)) {
-            nodep->v3error("Output port is connected to a constant pin, electrical short");
-        }
         // Use user1p on the PIN to indicate we created an assign for this pin
         if (!nodep->user1SetOnce()) {
             // Simplify it
@@ -514,6 +511,7 @@ public:
 	} else {
 	    // Make a new temp wire
             //if (1||debug()>=9) { pinp->dumpTree(cout,"-in_pin:"); }
+            V3Inst::checkOutputShort(pinp);
             AstNode* pinexprp = pinp->exprp()->unlinkFrBack();
             string newvarname = (string(pinVarp->isWritable() ? "__Vcellout" : "__Vcellinp")
                                  // Prevent name conflict if both tri & non-tri add signals
@@ -559,6 +557,19 @@ AstAssignW* V3Inst::pinReconnectSimple(AstPin* pinp, AstCell* cellp,
     return InstStatic::pinReconnectSimple(pinp, cellp, forTristate, alwaysCvt);
 }
 
+void V3Inst::checkOutputShort(AstPin* nodep) {
+    if (nodep->modVarp()->direction() == VDirection::OUTPUT) {
+        if (VN_IS(nodep->exprp(), Const)
+            || VN_IS(nodep->exprp(), Extend)
+            || (VN_IS(nodep->exprp(), Concat)
+                && (VN_IS(VN_CAST(nodep->exprp(), Concat)->lhsp(), Const)))) {
+            // Uses v3warn for error, as might be found multiple times
+            nodep->v3warn(E_PORTSHORT, "Output port is connected to a constant pin,"
+                          " electrical short");
+        }
+    }
+}
+
 //######################################################################
 // Inst class visitor
 

src/V3Inst.h

@@ -35,6 +35,7 @@ public:
     static void dearrayAll(AstNetlist* nodep);
     static AstAssignW* pinReconnectSimple(AstPin* pinp, AstCell* cellp,
                                           bool forTristate, bool alwaysCvt=false);
+    static void checkOutputShort(AstPin* nodep);
 };
 
 #endif // Guard

test_regress/t/t_lint_setout_bad.out

@@ -0,0 +1,2 @@
+%Error-PORTSHORT: t/t_lint_setout_bad.v:16: Output port is connected to a constant pin, electrical short
+%Error: Exiting due to

test_regress/t/t_lint_setout_bad.pl

@@ -15,9 +15,7 @@ compile(
     verilator_make_gcc => 0,
     make_top_shell => 0,
     make_main => 0,
-    expect =>
+    expect_filename => $Self->{golden_filename},
-'%Error: t/t_lint_setout_bad.v:\d+: Output port is connected to a constant pin, electrical short
-.*',
     );
 
 ok(1);

test_regress/t/t_lint_setout_bad_noinl.out

@@ -0,0 +1,2 @@
+%Error-PORTSHORT: t/t_lint_setout_bad.v:16: Output port is connected to a constant pin, electrical short
+%Error: Exiting due to

test_regress/t/t_lint_setout_bad_noinl.pl

@@ -17,9 +17,7 @@ compile(
     verilator_make_gcc => 0,
     make_top_shell => 0,
     make_main => 0,
-    expect =>
+    expect_filename => $Self->{golden_filename},
-'%Error: t/t_lint_setout_bad.v:\d+: Output port is connected to a constant pin, electrical short
-.*',
     );
 
 ok(1);

test_regress/t/t_lint_subout_bad.out

@@ -0,0 +1,4 @@
+%Error-PORTSHORT: t/t_lint_subout_bad.v:11: Output port is connected to a constant pin, electrical short
+%Error-PORTSHORT: t/t_lint_subout_bad.v:12: Output port is connected to a constant pin, electrical short
+%Error-PORTSHORT: t/t_lint_subout_bad.v:10: Output port is connected to a constant pin, electrical short
+%Error: Exiting due to

test_regress/t/t_lint_subout_bad.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(vlt_all => 1);
+
+compile(
+    # No --lint-only as got compile error
+    verilator_flags2 => ["--trace"],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
+

test_regress/t/t_lint_subout_bad.v

@@ -0,0 +1,16 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Wilson Snyder.
+
+// verilator lint_off UNDRIVEN
+
+module t();
+   wire sig;
+   sub sub0(.out(33'b0));
+   sub sub1(.out({32'b0, sig}));
+   sub sub2(.out({32'b1, sig}));
+endmodule
+
+module sub(output reg [32 : 0] out);
+endmodule