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Increase devel version as next release will be 4.200

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Wilson Snyder 2021-03-07 11:35:29 -05:00
parent 8df06a9f08
commit a9d61a8bff
2 changed files with 6 additions and 3 deletions
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7
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@ -2,8 +2,7 @@ Revision history for Verilator
The contributors that suggested a given feature are shown in []. Thanks! The contributors that suggested a given feature are shown in []. Thanks!
* Verilator 4.111 devel * Verilator 4.199 devel
(Next release version number will be 4.200)
** Add simulation context (VerilatedContext) to allow multiple fully independent ** Add simulation context (VerilatedContext) to allow multiple fully independent
models to be in the same process. Please see the updated examples. models to be in the same process. Please see the updated examples.
@ -13,6 +12,10 @@ The contributors that suggested a given feature are shown in []. Thanks!
**** --inhibit-sim is planned for deprecation, file a bug if this is still being used. **** --inhibit-sim is planned for deprecation, file a bug if this is still being used.
**** Fix range inheritance on port without data type (#2753). [Embedded Go]
**** Fix slice-assign overflow (#2803) (#2811). [David Turner]
* Verilator 4.110 2021-02-25 * Verilator 4.110 2021-02-25

2
configure.ac
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@ -7,7 +7,7 @@
#AC_INIT([Verilator],[#.### YYYY-MM-DD]) #AC_INIT([Verilator],[#.### YYYY-MM-DD])
#AC_INIT([Verilator],[#.### devel]) #AC_INIT([Verilator],[#.### devel])
AC_INIT([Verilator],[4.111 devel], AC_INIT([Verilator],[4.199 devel],
[https://verilator.org], [https://verilator.org],
[verilator],[https://verilator.org]) [verilator],[https://verilator.org])
# When releasing, also update header of Changes file # When releasing, also update header of Changes file