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https://github.com/verilator/verilator.git
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Improve automatic selection of logic for Dfg synthesis (#6370)
Reduce set of synthesized logic to be more in-line with what Dfg used to handle before + drivers of circular variables. This was always the intention but the previous algorithm was both a bit too eager, and also missed some circular variables. We can add back more heuristics based on performance measurements for non-circular logic later.
This commit is contained in:
Geza Lore
+181
-121
@@ -535,6 +535,7 @@ class AstToDfgSynthesize final {
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AstToDfgConverter<T_Scoped> m_converter; // The convert instance to use for each construct
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size_t m_nBranchCond = 0; // Sequence numbers for temporaries
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size_t m_nPathPred = 0; // Sequence numbers for temporaries
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DfgWorklist m_toRevert{m_dfg}; // We need a worklist for reverting synthesis
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// STATE - for current DfgLogic being synthesized
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DfgLogic* m_logicp = nullptr; // Current logic vertex we are synthesizing
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@@ -1587,46 +1588,102 @@ class AstToDfgSynthesize final {
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return true;
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}
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// Revert synthesis of the given DfgLogic
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void revert(DfgLogic& vtx) {
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for (DfgVertex* const p : vtx.synth()) VL_DO_DANGLING(p->unlinkDelete(m_dfg), p);
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vtx.synth().clear();
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}
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// Revert all logic driving the given unresolved driver, delete it,
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// and transitively the same for variables driven by the reverted logic.
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void revertTransivelyAndRemove(DfgUnresolved* vtxp, VDouble0& statCountr) {
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// The result variable will be driven from Ast code, mark as such
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vtxp->singleSink()->as<DfgVertexVar>()->setHasModWrRefs();
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// Gather all logic driving this unresolved driver
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std::vector<DfgLogic*> logicps;
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logicps.reserve(vtxp->nInputs());
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vtxp->foreachSource([&](DfgVertex& src) {
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if (DfgLogic* const p = src.cast<DfgLogic>()) logicps.emplace_back(p);
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return false;
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});
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// Delete the unresolved driver
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VL_DO_DANGLING(vtxp->unlinkDelete(m_dfg), vtxp);
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// Transitively for the rest
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for (DfgLogic* const logicp : logicps) {
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if (!logicp->synth().empty()) {
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// Revert all DfgLogic in m_toRevert, or DfgLogic driving the DfgUnresolved
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// vertices in m_toRevert, and transitively the same for any DfgUnresolved
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// driven by the reverted DfgLogic. Delete all DfgUnresolved involed.
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void revert(VDouble0& statCountr) {
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m_toRevert.foreach([&](DfgVertex& vtx) {
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// Process DfgLogic
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if (DfgLogic* const vtxp = vtx.cast<DfgLogic>()) {
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UASSERT_OBJ(vtxp->selectedForSynthesis(), vtxp, "Shouldn't reach here unselected");
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// Revert this logic
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UASSERT_OBJ(!vtxp->reverted(), vtxp, "Should be reverting now");
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++statCountr;
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revert(*logicp);
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for (DfgVertex* const p : vtxp->synth()) VL_DO_DANGLING(p->unlinkDelete(m_dfg), p);
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vtxp->synth().clear();
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vtxp->setReverted();
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// Add all DfgUnresolved it drives to the work list
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vtxp->foreachSink([&](DfgVertex& snk) {
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m_toRevert.push_front(*snk.as<DfgUnresolved>());
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return false;
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});
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return;
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}
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while (DfgVertex* const sinkp = logicp->firtsSinkp()) {
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revertTransivelyAndRemove(sinkp->as<DfgUnresolved>(), statCountr);
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// Process DfgUnresolved
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if (DfgUnresolved* const vtxp = vtx.cast<DfgUnresolved>()) {
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// The result variable will be driven from Ast code, mark as such
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vtxp->singleSink()->as<DfgVertexVar>()->setHasModWrRefs();
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// Add all driving DfgLogic to the work list
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vtxp->foreachSource([&](DfgVertex& src) {
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DfgLogic* const lp = src.cast<DfgLogic>();
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if (lp && !lp->reverted()) m_toRevert.push_front(*lp);
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return false;
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});
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// Delete the DfgUnresolved driver
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VL_DO_DANGLING(vtxp->unlinkDelete(m_dfg), vtxp);
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return;
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}
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}
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// There should be nothing else on the worklist
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vtx.v3fatalSrc("Unexpected vertex type");
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});
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}
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// Synthesize all of the given vertices
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void main(const std::vector<DfgLogic*>& logicps) {
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void main() {
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//-------------------------------------------------------------------
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UINFO(5, "Step 1: Attempting to synthesize each of the given DfgLogic");
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for (DfgLogic* const logicp : logicps) {
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UINFO(5, "Step 0: Remove all DfgLogic not selected for synthesis");
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for (DfgVertex* const vtxp : m_dfg.opVertices().unlinkable()) {
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// Only processing DfgUnresolved
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if (!vtxp->is<DfgUnresolved>()) continue;
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bool anySelected = false;
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bool anyUnselected = false;
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vtxp->foreachSource([&](DfgVertex& src) {
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const DfgLogic& logic = *src.as<DfgLogic>();
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if (logic.selectedForSynthesis()) {
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anySelected = true;
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} else {
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anyUnselected = true;
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}
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return false;
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});
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// There should be a driver
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UASSERT_OBJ(anySelected || anyUnselected, vtxp, "'DfgUnresolved' with no driver");
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// All drivers should be selected or all should be unselected
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UASSERT_OBJ(!(anySelected && anyUnselected), vtxp, "Invalid 'DfgLogic' selection");
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// If all drivers are unselected, delete this DfgUnresolved here
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if (anyUnselected) {
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// The result variable will be driven from Ast code, mark as such
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vtxp->singleSink()->as<DfgVertexVar>()->setHasModWrRefs();
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VL_DO_DANGLING(vtxp->unlinkDelete(m_dfg), vtxp);
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}
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}
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for (DfgVertex* const vtxp : m_dfg.opVertices().unlinkable()) {
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// Only processing DfgLogic
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DfgLogic* const logicp = vtxp->cast<DfgLogic>();
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if (!logicp) continue;
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if (logicp->selectedForSynthesis()) continue;
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// There should be no sinks left for unselected DfgLogic, delete them here
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UASSERT_OBJ(!logicp->hasSinks(), vtxp, "Unselected 'DfgLogic' with sinks remaining");
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// Input variables will be read in Ast code, mark as such
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logicp->foreachSource([](DfgVertex& src) {
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src.as<DfgVertexVar>()->setHasModRdRefs();
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return false;
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});
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VL_DO_DANGLING(logicp->unlinkDelete(m_dfg), logicp);
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}
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debugDump("synth-selected");
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//-------------------------------------------------------------------
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UINFO(5, "Step 1: Attempting to synthesize each of the selected DfgLogic");
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for (DfgVertex& vtx : m_dfg.opVertices()) {
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DfgLogic* const logicp = vtx.cast<DfgLogic>();
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if (!logicp) continue;
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// We should only have DfgLogic remaining that was selected for synthesis
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UASSERT_OBJ(logicp->selectedForSynthesis(), logicp, "Unselected DfgLogic remains");
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// Debug aid
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if (VL_UNLIKELY(s_dfgSynthDebugLimit)) {
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if (s_dfgSynthDebugCount == s_dfgSynthDebugLimit) break;
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@@ -1641,27 +1698,18 @@ class AstToDfgSynthesize final {
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}
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}
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// Synthesize it, revert partial construction if failed
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if (!synthesize(*logicp)) revert(*logicp);
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// Synthesize it, if failed, enqueue for reversion
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if (!synthesize(*logicp)) {
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logicp->setNonSynthesizable();
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m_toRevert.push_front(*logicp);
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}
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}
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debugDump("synth-converted");
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//-------------------------------------------------------------------
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UINFO(5, "Step 2: Revert drivers of variables with unsynthesizeable drivers");
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// We do this as the variables might be multi-driven, we just can't know at this point
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for (const DfgVertexVar& var : m_dfg.varVertices()) {
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if (!var.srcp()) continue;
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DfgUnresolved* const unresolvedp = var.srcp()->cast<DfgUnresolved>();
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if (!unresolvedp) break; // Stop when reached the synthesized temporaries
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// Check if any driver have failed to synthesize
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const bool failed = unresolvedp->foreachSource([&](DfgVertex& src) {
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DfgLogic* const driverp = src.cast<DfgLogic>();
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return driverp && driverp->synth().empty();
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});
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// Revert all logic involved
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if (failed) revertTransivelyAndRemove(unresolvedp, m_ctx.m_synt.revertNonSyn);
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}
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// We do this as the variables might be multi-driven, we can't know if synthesis failed
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revert(m_ctx.m_synt.revertNonSyn);
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debugDump("synth-reverted");
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//-------------------------------------------------------------------
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@@ -1689,6 +1737,7 @@ class AstToDfgSynthesize final {
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if (normalizeDrivers(var, drivers)) return makeSplice(var, drivers);
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// If mutlidriven, record and ignore
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multidrivenps.emplace_back(&var);
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m_toRevert.push_front(*unresolvedp);
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return nullptr;
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}();
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// Bail if multidriven
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@@ -1697,16 +1746,10 @@ class AstToDfgSynthesize final {
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const bool newEntry = resolvedDrivers.emplace(&var, resolvedp).second;
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UASSERT_OBJ(newEntry, &var, "Dupliacte driver");
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}
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// Mark as multidriven for future DFG runs - here, so we get all warnings above
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for (const DfgVertexVar* const vtxp : multidrivenps) vtxp->varp()->setDfgMultidriven();
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// Revert and remove drivers of multi-driven variables
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for (const DfgVertexVar* const vtxp : multidrivenps) {
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// Mark as multidriven for future DFG runs - here, so we get all warning before
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vtxp->varp()->setDfgMultidriven();
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// Might not have a driver if transitively removed on an earlier iteration
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if (!vtxp->srcp()) continue;
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// Revert all logic involved
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DfgUnresolved* const unresolvedp = vtxp->srcp()->as<DfgUnresolved>();
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revertTransivelyAndRemove(unresolvedp, m_ctx.m_synt.revertMultidrive);
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}
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revert(m_ctx.m_synt.revertMultidrive);
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// Replace all DfgUnresolved with the resolved drivers
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for (const DfgVertexVar& var : m_dfg.varVertices()) {
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if (!var.srcp()) continue;
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@@ -1720,7 +1763,7 @@ class AstToDfgSynthesize final {
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debugDump("synth-resolved");
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//-------------------------------------------------------------------
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UINFO(5, "Step 4: Remove all DfgLogic and DfgUnresolved");
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UINFO(5, "Step 4: Remove all remaining DfgLogic and DfgUnresolved");
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for (DfgVertex* const vtxp : m_dfg.opVertices().unlinkable()) {
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// Previous step should have removed all DfgUnresolved
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UASSERT_OBJ(!vtxp->is<DfgUnresolved>(), vtxp, "DfgUnresolved remains");
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@@ -1776,17 +1819,30 @@ class AstToDfgSynthesize final {
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}
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}
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debugDump("synth-rmsplice");
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}
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//-------------------------------------------------------------------
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// CONSTRUCTOR
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AstToDfgSynthesize(DfgGraph& dfg, V3DfgSynthesisContext& ctx)
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: m_dfg{dfg}
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, m_ctx{ctx}
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, m_converter{dfg, ctx} {
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main();
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}
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public:
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static void apply(DfgGraph& dfg, V3DfgSynthesisContext& ctx) {
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AstToDfgSynthesize{dfg, ctx};
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// Final step outside, as both AstToDfgSynthesize and removeUnused used DfgUserMap
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UINFO(5, "Step 6: Remove all unused vertices");
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V3DfgPasses::removeUnused(m_dfg);
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debugDump("synth-rmunused");
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V3DfgPasses::removeUnused(dfg);
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if (dumpDfgLevel() >= 9) dfg.dumpDotFilePrefixed(ctx.prefix() + "synth-rmunused");
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// No operation vertex should have multiple sinks. Cyclic decomoposition
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// depends on this and it can easily be ensured by using temporaries.
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// Also, all sources should be connected at this point
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if (v3Global.opt.debugCheck()) {
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for (DfgVertex& vtx : m_dfg.opVertices()) {
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for (DfgVertex& vtx : dfg.opVertices()) {
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UASSERT_OBJ(!vtx.hasMultipleSinks(), &vtx, "Operation has multiple sinks");
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for (size_t i = 0; i < vtx.nInputs(); ++i) {
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UASSERT_OBJ(vtx.inputp(i), &vtx, "Unconnected source operand");
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@@ -1794,79 +1850,83 @@ class AstToDfgSynthesize final {
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}
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}
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}
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// CONSTRUCTOR
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AstToDfgSynthesize(DfgGraph& dfg, const std::vector<DfgLogic*>& logicps,
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V3DfgSynthesisContext& ctx)
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: m_dfg{dfg}
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, m_ctx{ctx}
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, m_converter{dfg, ctx} {}
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public:
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static void apply(DfgGraph& dfg, const std::vector<DfgLogic*>& logicps,
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V3DfgSynthesisContext& ctx) {
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AstToDfgSynthesize{dfg, logicps, ctx}.main(logicps);
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}
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};
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void V3DfgPasses::synthesize(DfgGraph& dfg, V3DfgContext& ctx) {
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// The vertices to synthesize
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std::vector<DfgLogic*> logicps;
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// Decide which DfgLogic to attempt to synthesize
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static void dfgSelectLogicForSynthesis(DfgGraph& dfg) {
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// If we are told to synthesize everything, we will do so ...
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if (v3Global.opt.fDfgSynthesizeAll()) {
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// If we are told to synthesize everything, we will do so ...
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for (DfgVertex& vtx : dfg.opVertices()) {
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if (DfgLogic* const logicp = vtx.cast<DfgLogic>()) logicps.emplace_back(logicp);
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if (DfgLogic* const logicp = vtx.cast<DfgLogic>()) logicp->setSelectedForSynthesis();
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}
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} else {
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// Otherwise figure out which vertices are worth synthesizing.
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return;
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}
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// Find cycles
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// Otherwise figure out which vertices are likely worth synthesizing.
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// Bather circular variables
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std::vector<DfgVertexVar*> circularVarps;
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{
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DfgUserMap<uint64_t> scc = dfg.makeUserMap<uint64_t>();
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V3DfgPasses::colorStronglyConnectedComponents(dfg, scc);
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// First, gather variables, we will then attempt to synthesize all their drivers
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std::vector<DfgVertexVar*> varps;
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for (DfgVertexVar& var : dfg.varVertices()) {
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// Can ignore variables with no drivers
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if (!var.srcp()) continue;
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// Circular variable - synthesize
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if (scc.at(var)) {
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varps.emplace_back(&var);
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continue;
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}
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// Must be driven from a DfgUnresolved at this point, pick it up
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const DfgUnresolved* const unresolvedp = var.srcp()->as<DfgUnresolved>();
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// Inspect drivers to figure out if we should synthesize them
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const bool doIt = unresolvedp->foreachSource([&](const DfgVertex& src) {
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const DfgLogic* const logicp = src.as<DfgLogic>();
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// Synthesize continuous assignments (this is the earlier behaviour).
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// Synthesize always blocks with no more than 4 basic blocks and 4 edges
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// These are usually simple branches (if (rst) ... else ...), or close to it
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return VN_IS(logicp->nodep(), AssignW) //
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|| (logicp->cfg().nBlocks() <= 4 && logicp->cfg().nEdges() <= 4);
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});
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if (doIt) varps.emplace_back(&var);
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if (!scc.at(var)) continue;
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// This is a circular variable
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circularVarps.emplace_back(&var);
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}
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}
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// Gather all drivers of the selected variables
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const VNUser2InUse user2InUse; // AstNode (logic) -> bool: already collected
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for (const DfgVertexVar* const varp : varps) {
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varp->srcp()->as<DfgUnresolved>()->foreachSource([&](DfgVertex& source) {
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DfgLogic* const logicp = source.as<DfgLogic>();
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if (!logicp->nodep()->user2Inc()) logicps.emplace_back(logicp);
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// We need to expand the selection to cover all drivers, use a work list
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DfgWorklist worklist{dfg};
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// Synthesize all drivers of circular variables
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for (const DfgVertexVar* const varp : circularVarps) {
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varp->srcp()->as<DfgUnresolved>()->foreachSource([&](DfgVertex& driver) {
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worklist.push_front(*driver.as<DfgLogic>());
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return false;
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});
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}
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// Synthesize all AssignW and simple blocks driving exactly one variable
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// This is approximately the old default behaviour of Dfg
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for (DfgVertex& vtx : dfg.opVertices()) {
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DfgLogic* const logicp = vtx.cast<DfgLogic>();
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if (!logicp) continue;
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if (VN_IS(logicp->nodep(), AssignW)) {
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worklist.push_front(*logicp);
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continue;
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}
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const CfgGraph& cfg = logicp->cfg();
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if (!logicp->hasMultipleSinks() && cfg.nBlocks() <= 4 && cfg.nEdges() <= 4) {
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worklist.push_front(*logicp);
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}
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}
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// Now expand to cover all logic driving the same set of variables and mark
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worklist.foreach([&](DfgVertex& vtx) {
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DfgLogic& logic = *vtx.as<DfgLogic>();
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UASSERT_OBJ(!logic.selectedForSynthesis(), &vtx, "Should not be visited twice");
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// Mark as selected for synthesis
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logic.setSelectedForSynthesis();
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// Enqueue all other logic driving the same variables as this one
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logic.foreachSink([&](DfgVertex& sink) {
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sink.as<DfgUnresolved>()->foreachSource([&](DfgVertex& sibling) {
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DfgLogic& siblingLogic = *sibling.as<DfgLogic>();
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if (!siblingLogic.selectedForSynthesis()) worklist.push_front(siblingLogic);
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return false;
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});
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}
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}
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return false;
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});
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});
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}
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// Synthesize them - also removes un-synthesized DfgLogic, so must run even if logicps.empty()
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void V3DfgPasses::synthesize(DfgGraph& dfg, V3DfgContext& ctx) {
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// Select which DfgLogic to attempt to synthesize
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dfgSelectLogicForSynthesis(dfg);
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// Synthesize them - also removes un-synthesized DfgLogic, so must run even if nothing selected
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if (dfg.modulep()) {
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AstToDfgSynthesize</* T_Scoped: */ false>::apply(dfg, logicps, ctx.m_synthContext);
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AstToDfgSynthesize</* T_Scoped: */ false>::apply(dfg, ctx.m_synthContext);
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} else {
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AstToDfgSynthesize</* T_Scoped: */ true>::apply(dfg, logicps, ctx.m_synthContext);
|
||||
AstToDfgSynthesize</* T_Scoped: */ true>::apply(dfg, ctx.m_synthContext);
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user