Fix "output reg name=expr;" syntax error. [Martin Scharrer]

git-svn-id: file://localhost/svn/verilator/trunk/verilator@1027 77ca24e4-aefa-0310-84f0-b9a241c72d87

Changes

@@ -7,6 +7,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Add error message when modules have duplicate names. [Stefan Thiede]
 
+**** Fix "output reg name=expr;" syntax error.  [Martin Scharrer]
+
 **** Fix multiple .v files being read in random order. [Stefan Thiede]
 
 * Verilator 3.661 2008/04/04

src/verilog.y

@@ -376,7 +376,7 @@ class AstSenTree;
 //	Trailing E indicates this type may have empty match
 %type<modulep>	modHdr
 %type<nodep>	modPortsE portList port
-%type<nodep>	portV2kArgs portV2kList portV2kSecond portV2kSig
+%type<nodep>	portV2kArgs portV2kList portV2kSecond portV2kInit portV2kSig
 %type<nodep>	portV2kDecl portDecl varDecl
 %type<nodep>	modParArgs modParSecond modParDecl modParList modParE
 %type<nodep>	modItem modItemList modItemListE modOrGenItem
@@ -384,7 +384,7 @@ class AstSenTree;
 %type<nodep>	genItem genItemList genItemBegin genItemBlock genTopBlock genCaseListE genCaseList
 %type<nodep>	dlyTerm minTypMax
 %type<fileline> delay
-%type<varp>	sigAndAttr sigId sigIdRange sigList regsig regsigList regSigId
+%type<varp>	sigAndAttr sigId sigIdRange regsig regsigList regSigId
 %type<varp>	netSig netSigList
 %type<rangep>	rangeListE regrangeE anyrange rangeList delayrange portRangeE
 %type<varp>	param paramList
@@ -513,7 +513,12 @@ portV2kList:	portV2kSecond				{ $$ = $1; }
 
 // Called only after a comma in a v2k list, to allow parsing "input a,b"
 portV2kSecond:	portV2kDecl				{ $$ = $1; }
-	|	portV2kSig				{ $$ = $1; }
+	|	portV2kInit				{ $$ = $1; }
+	;
+
+portV2kInit:	portV2kSig				{ $$=$1; }
+	|	portV2kSig '=' expr			
+			{ $$=$1; $$->addNext(new AstInitial($2,new AstAssign($2, new AstVarRef($2,V3Parse::s_varAttrp->name(),true), $3))); }
 	;
 
 portV2kSig:	sigAndAttr				{ $$=$1; $$->addNext(new AstPort(CRELINE(),V3Parse::s_pinNum++, V3Parse::s_varAttrp->name())); }
@@ -530,15 +535,11 @@ regsigList:	regsig  				{ $$ = $1; }
 	|	regsigList ',' regsig		       	{ $$ = $1;$1->addNext($3); }
 	;
 
-portV2kDecl:	varRESET varInput  v2kVarDeclE signingE regrangeE portV2kSig	{ $$ = $6; }
+portV2kDecl:	varRESET portDirection v2kVarDeclE signingE regrangeE portV2kInit	{ $$ = $6; }
-	|	varRESET varInout  v2kVarDeclE signingE regrangeE portV2kSig	{ $$ = $6; }
-	|	varRESET varOutput v2kVarDeclE signingE regrangeE portV2kSig	{ $$ = $6; }
 	;
 
 // IEEE: port_declaration - plus ';'
-portDecl:	varRESET varInput  v2kVarDeclE signingE regrangeE  sigList ';'	{ $$ = $6; }
+portDecl:	varRESET portDirection v2kVarDeclE signingE regrangeE  regsigList ';'	{ $$ = $6; }
-     	|	varRESET varInout  v2kVarDeclE signingE regrangeE  sigList ';'	{ $$ = $6; }
-     	|	varRESET varOutput v2kVarDeclE signingE regrangeE  sigList ';'	{ $$ = $6; }
 	;
 
 varDecl:	varRESET varReg     signingE regrangeE  regsigList ';'	{ $$ = $5; }
@@ -568,11 +569,12 @@ varGenVar:	yGENVAR					{ VARDECL(GENVAR); }
 varReg:		yREG					{ VARDECL(REG); }
 	|	yINTEGER				{ VARDECL(INTEGER); }
 	;
-varInput:	yINPUT					{ VARIO(INPUT); }
+
-	;
+//IEEE: port_direction
-varOutput:	yOUTPUT					{ VARIO(OUTPUT); }
+portDirection:	yINPUT					{ VARIO(INPUT); }
-	;
+	|	yOUTPUT					{ VARIO(OUTPUT); }
-varInout:	yINOUT					{ VARIO(INOUT); }
+	|	yINOUT					{ VARIO(INOUT); }
+//	|	yREF					{ VARIO(REF); }
 	;
 
 // IEEE: signing - plus empty
@@ -731,10 +733,6 @@ regSigId:	yaID rangeListE				{ $$ = V3Parse::createVariable(CRELINE(), *$1, $2);
 sigId:		yaID					{ $$ = V3Parse::createVariable(CRELINE(), *$1, NULL); }
 	;
 
-sigList:	sigAndAttr				{ $$ = $1; }
-	|	sigList ',' sigAndAttr			{ $$ = $1; $1->addNext($3); }
-	;
-
 regsig:		regSigId sigAttrListE			{}
 	;
 

test_regress/t/.gitattributes

@@ -0,0 +1 @@
+t_dos*.pl	-crlf

test_regress/t/t_inst_v2k.v

@@ -23,8 +23,10 @@ module t (/*AUTOARG*/
 `endif
 
    wire [7:0]		osizedreg;		// From sub of t_inst_v2k_sub.v
+   wire [1:0]		tied;
+   wire [3:0]		tied_also;
 
-   hello hsub;
+   hello hsub (.tied_also);
 
    t_inst_v2k_sub sub
      (
@@ -33,6 +35,7 @@ module t (/*AUTOARG*/
       // verilator lint_off IMPLICIT
       .oonewire				(oonewire),
       // verilator lint_on IMPLICIT
+      .tied				(tied[1:0]),
       // Inputs
       .isizedwire			(isizedwire[7:0]),
       .ionewire				(ionewire));
@@ -49,6 +52,8 @@ module t (/*AUTOARG*/
 	    if (high != 2'b11) $stop;
 	    if (oonewire !== 1'b1) $stop;
 	    if (isizedwire !== 8'd8) $stop;
+	    if (tied != 2'b10) $stop;
+	    if (tied_also != 4'b1010) $stop;
 	    $write("*-* All Finished *-*\n");
 	    $finish;
 	 end
@@ -57,8 +62,10 @@ module t (/*AUTOARG*/
 
 endmodule
 
-module hello;
+module hello(tied_also);
    initial $write ("Hello\n");
+   output reg [3:0] tied_also = 4'b1010;
+
 endmodule
 
 // Local Variables:

test_regress/t/t_inst_v2k_sub.vi

@@ -1,4 +1,4 @@
-// $Id:$ -*- Verilog -*-
+// $Id$ -*- Verilog -*-
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -10,7 +10,8 @@ module t_inst_v2k_sub
    output reg [7:0] osizedreg,
    output wire oonewire /*verilator public*/,
    input [7:0] isizedwire,
-   input wire ionewire
+   input wire ionewire,
+   output reg [1:0] tied = 2'b10
    );
 
    assign oonewire = ionewire;