Fix evaluation of chained parameter functions, bug684.

Changes

@@ -5,6 +5,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 * Verilator 3.854 devel
 
+****  Fix evaluation of chained parameter functions, bug684. [Ted Campbell]
+
 ****  Fix multiple VPI variable callbacks, bug679. [Rich Porter]
 
 ****  Fix vpi_get of vpiSize, bug680. [Rich Porter]

src/V3Simulate.h

@@ -603,20 +603,25 @@ private:
 	if (m_params) { V3Width::widthParamsEdit(funcp); } funcp=NULL; // Make sure we've sized the function
 	funcp = nodep->taskp()->castNodeFTask(); if (!funcp) nodep->v3fatalSrc("Not linked");
 	// Apply function call values to function
-	// Note we'd need a stack if we allowed recursive functions!
 	V3TaskConnects tconnects = V3Task::taskConnects(nodep, nodep->taskp()->stmtsp());
+	// Must do this in two steps, eval all params, then apply them
+	// Otherwise chained functions may have the wrong results
 	for (V3TaskConnects::iterator it=tconnects.begin(); it!=tconnects.end(); ++it) {
 	    AstVar* portp = it->first;
 	    AstNode* pinp = it->second->exprp();
-	    if (pinp==NULL) {
+	    if (pinp) {  // Else too few arguments in function call - ignore it
-		// Too few arguments in function call - ignore it
-	    } else {
 		if (portp->isOutput()) {
 		    clearOptimizable(portp,"Language violation: Outputs not allowed in constant functions");
 		    return;
 		}
 		// Evaluate pin value
 		pinp->accept(*this);
+	    }
+	}
+	for (V3TaskConnects::iterator it=tconnects.begin(); it!=tconnects.end(); ++it) {
+	    AstVar* portp = it->first;
+	    AstNode* pinp = it->second->exprp();
+	    if (pinp) {  // Else too few arguments in function call - ignore it
 		// Apply value to the function
 		if (!m_checkOnly && optimizable()) {
 		    newNumber(portp)->opAssign(*fetchNumber(pinp));

test_regress/t/t_param_chain.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_param_chain.v

@@ -0,0 +1,36 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2013 by Wilson Snyder.
+
+module t (/*AUTOARG*/);
+
+    function integer max2;
+       input integer x;
+       input integer y;
+       begin
+	  begin : blk
+	     automatic int temp;
+	     temp = x;
+	  end
+       end
+       max2 = ( x > y ) ? x : y;
+    endfunction
+
+    function integer max4;
+       input integer x;
+       input integer y;
+       input integer z;
+       input integer w;
+       // MAX2 is used multiple times
+       max4 = max2( max2( x, y ), max2( z, w ) );
+    endfunction
+
+   localparam  MAX4 = max4( 1, 1, 0, 0 );
+
+   initial begin
+      if (MAX4 != 1) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule