Fix error on improperly widthed default function, bug984.

Changes

@@ -9,6 +9,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 **    Add --relative-includes. [Rob Stoddard]
 
+****  Fix error on improperly widthed default function, bug984. [Todd Strader]
+
 ****  Fix 2009 localparam syntax, msg2139. [Galen Seitz]
 
 ****  Fix ugly interface-to-non-interface errors, bug1112. [Johan Bjork]

src/V3Width.cpp

@@ -2806,11 +2806,11 @@ private:
 	if (extendRule == EXTEND_OFF) return;
 	AstConst* constp = nodep->castConst();
 	int expWidth = expDTypep->width();
-	if (constp && !nodep->isSigned()) {
+	if (constp && !constp->num().isNegative()) {
 	    // Save later constant propagation work, just right-size it.
 	    V3Number num (nodep->fileline(), expWidth);
 	    num.opAssign(constp->num());
-	    num.isSigned(expDTypep->isSigned());
+	    num.isSigned(false);
 	    AstNode* newp = new AstConst(nodep->fileline(), num);
 	    constp->replaceWith(newp);
 	    pushDeletep(constp); VL_DANGLING(constp); VL_DANGLING(nodep);

test_regress/t/t_func_default_warn.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    verilator_flags2 => ["-Wno-WIDTH"],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_func_default_warn.v

@@ -0,0 +1,28 @@
+// DESCRIPTION: Verilator: Test for warning (not error) on improperly width'ed
+// default function argument
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2015 by Todd Strader.
+
+function logic foo
+  (
+   // Intentionally provide a non-width'ed default value
+   // This should warn, not error out
+   input logic x = 0
+   );
+   return x;
+endfunction
+
+module t (/*AUTOARG*/);
+   logic foo_val;
+
+   initial begin
+      foo_val = foo();
+      if (foo_val != 1'b0) $stop;
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule
+