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Backout (#4710) due to leak

This commit is contained in:
Wilson Snyder 2024-02-04 18:13:22 -05:00
parent f13f2296de
commit a6ad85244f
4 changed files with 2 additions and 61 deletions
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1
Changes
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@ -25,7 +25,6 @@ Verilator 5.021 devel
* Support SystemC 3.0.0 public review version (#4805) (#4807). [Anthony Donlon] * Support SystemC 3.0.0 public review version (#4805) (#4807). [Anthony Donlon]
* Support parsing anonymous primitive instantiations (#4809). [Anthony Donlon] * Support parsing anonymous primitive instantiations (#4809). [Anthony Donlon]
* Fix to not emit already waived warnings in waiver output (#4574) (#4818). [Jonathan Schröter] * Fix to not emit already waived warnings in waiver output (#4574) (#4818). [Jonathan Schröter]
* Fix `this` in member initialization (#4710). [eliasphanna]
* Fix localparam elaboration (#3858) (#4794). [Andrew Nolte] * Fix localparam elaboration (#3858) (#4794). [Andrew Nolte]
* Fix lint_off disables on preprocessor warnings (#4703). [Srinivasan Venkataramanan] * Fix lint_off disables on preprocessor warnings (#4703). [Srinivasan Venkataramanan]
* Fix $time not rounding up (#4790) (#4792). [Paul Wright] * Fix $time not rounding up (#4790) (#4792). [Paul Wright]

4
src/V3LinkDot.cpp
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@ -2208,9 +2208,9 @@ class LinkDotResolveVisitor final : public VNVisitor {
} }
VSymEnt* getThisClassSymp() { VSymEnt* getThisClassSymp() {
VSymEnt* classSymp = m_ds.m_dotSymp; VSymEnt* classSymp = m_ds.m_dotSymp;
while (classSymp && !VN_IS(classSymp->nodep(), Class)) { do {
classSymp = classSymp->parentp(); classSymp = classSymp->parentp();
} } while (classSymp && !VN_IS(classSymp->nodep(), Class));
return classSymp; return classSymp;
} }
void importImplementsClass(AstClass* implementsClassp, VSymEnt* interfaceSymp, void importImplementsClass(AstClass* implementsClassp, VSymEnt* interfaceSymp,

21
test_regress/t/t_0.pl
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@ -1,21 +0,0 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
compile(
);
execute(
check_finished => 1,
);
ok(1);
1;

37
test_regress/t/t_0.v
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@ -1,37 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2024 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
interface class ICls;
pure virtual function string get();
endclass
class Cls;
string name;
ICls icls;
function new(string name, ICls icls);
this.name = name;
this.icls = icls;
endfunction
endclass
class Testcase implements ICls;
Cls cls = new("test_class", this);
virtual function string get();
return "In ICls";
endfunction
endclass
module t(/*AUTOARG*/);
initial begin
Testcase test;
test = new;
if (test.cls.name != "test_class") $stop;
if (test.cls.icls.get() != "In ICls") $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule