Fix clocking-block sample of unpacked array (#7612) (#7613)

Fixes #7612.

src/V3Slice.cpp

@@ -206,6 +206,11 @@ class SliceVisitor final : public VNVisitor {
                                          : elemIdx));
             newp = new AstArraySel{nodep->fileline(), snodep->fromp()->cloneTree(false, needPure),
                                    leOffset};
+        } else if (const AstSampled* const snodep = VN_CAST(nodep, Sampled)) {
+            UINFO(9, "  cloneSliceSel(" << elements << "," << elemIdx << ") " << nodep);
+            AstNodeExpr* const exprp = VN_AS(snodep->exprp(), NodeExpr);
+            AstNodeExpr* const selp = cloneAndSel(exprp, elements, elemIdx, needPure);
+            return new AstSampled{nodep->fileline(),selp};
         } else if (AstExprStmt* const snodep = VN_CAST(nodep, ExprStmt)) {
             UINFO(9, "  cloneExprStmt(" << elements << "," << elemIdx << ") " << nodep);
             AstNodeExpr* const resultSelp

test_regress/t/t_clocking_sampled_unpacked.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=["--binary"])
+
+test.execute()
+
+test.passes()

test_regress/t/t_clocking_sampled_unpacked.v

@@ -0,0 +1,29 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Nikolai Kumar
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+  logic clk = 0;
+  logic [1:0] data[1:0];
+  logic [1:0] snap[1:0];
+
+  clocking cb @(posedge clk);
+    input data;
+  endclocking
+
+  always @(cb) snap <= cb.data;
+
+  always #5 clk = ~clk;
+
+  initial begin
+    data[0] = 2'd1;
+    data[1] = 2'd2;
+    @(posedge clk);
+    @(posedge clk);
+    if (snap[0] !== 2'd1 || snap[1] !==2'd2) $stop;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule