update test and golden for split_var
This commit is contained in:
Yutetsu TAKATSUKASA
parent
20b59f381d
commit
a67c47e8a9
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@ -1,52 +1,201 @@
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module barshift #(parameter depth = 2, localparam width = 2**depth) (
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// If split_var pragma is removed, UNOPTFLAT appears.
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module barshift_1d_unpacked #(parameter depth = 2, localparam width = 2**depth) (
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input [width-1:0] in, input [depth-1:0] shift, output [width-1:0]out);
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// If the following split_array var is removed, ALWCOMBORDER and UNOPTFLAT appear.
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logic [width-1:0] tmp[depth-2:-2]; /*verilator split_var*/
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generate
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for(genvar i = 0; i < depth; ++i) begin
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always_comb
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if (shift[i]) begin
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tmp[i+1-2] = {tmp[i-2][(1 << i)-1:0], tmp[i-2][width-1:(2**i)]};
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end else begin
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tmp[i + 1 - 2] = tmp[i-2];
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localparam offset = -3;
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logic [width-1:0] tmp[depth+offset:offset]; /*verilator split_var*/
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generate
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for(genvar i = 0; i < depth; ++i) begin
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always_comb
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if (shift[i]) begin
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tmp[i+1+offset] = {tmp[i+offset][(1 << i)-1:0], tmp[i+offset][width-1:(2**i)]};
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end else begin
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tmp[i+1+offset] = tmp[i+offset];
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end
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end
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end
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endgenerate
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assign tmp[0-2] = in;
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assign out = tmp[depth-2];
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endgenerate
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assign tmp[0+offset] = in;
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assign out = tmp[depth+offset];
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endmodule
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module barshift_1d_unpacked_struct0 #(parameter depth = 2, localparam width = 2**depth) (
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input [width-1:0] in, input [depth-1:0] shift, output [width-1:0]out);
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localparam offset = 1;
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typedef struct packed { logic [width-1:0] data; } data_type;
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data_type tmp[depth+offset:offset]; /*verilator split_var*/
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generate
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for(genvar i = 0; i < depth; ++i) begin
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always_comb
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if (shift[i]) begin
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tmp[i+1+offset] = {tmp[i+offset][(1 << i)-1:0], tmp[i+offset][width-1:(2**i)]};
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end else begin
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tmp[i+1+offset] = tmp[i+offset];
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end
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end
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endgenerate
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assign tmp[0+offset] = in;
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assign out = tmp[depth+offset];
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endmodule
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module barshift_1d_unpacked_struct1 #(parameter depth = 2, localparam width = 2**depth) (
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input [width-1:0] in, input [depth-1:0] shift, output [width-1:0]out);
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localparam offset = 2;
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typedef struct packed { int data; } data_type;
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data_type tmp[depth+offset:offset]; /*verilator split_var*/
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localparam [32-width-1:0] pad = 0;
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generate
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for(genvar i = 0; i < depth; ++i) begin
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always_comb
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if (shift[i]) begin
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tmp[i+1+offset] = {pad, tmp[i+offset][(1 << i)-1:0], tmp[i+offset][width-1:(2**i)]};
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end else begin
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tmp[i+1+offset] = tmp[i+offset];
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end
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end
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endgenerate
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assign tmp[0+offset] = {pad, in};
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assign out = tmp[depth+offset][width-1:0];
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endmodule
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module barshift_2d_packed_array #(parameter depth = 2, localparam width = 2**depth) (
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input [width-1:0] in, input [depth-1:0] shift, output [width-1:0]out);
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localparam offset = -2;
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/*verilator lint_off LITENDIAN*/
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reg [offset:depth+offset][width-1:0] tmp; /*verilator split_var*/
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/*verilator lint_on LITENDIAN*/
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generate
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for(genvar i = 0; i < depth; ++i) begin
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always_comb
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/*verilator lint_off ALWCOMBORDER*/
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if (shift[i]) begin
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tmp[i+1+offset] = {tmp[i+offset][(1 << i)-1:0], tmp[i+offset][width-1:(2**i)]};
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end else begin
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tmp[i+1+offset][1:0] = tmp[i+offset][1:0];
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tmp[i+1+offset][width-1:2] = tmp[i+offset][width-1:2];
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end
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/*verilator lint_on ALWCOMBORDER*/
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end
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endgenerate
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assign tmp[0+offset] = in;
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assign out = tmp[depth+offset];
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endmodule
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module barshift_2d_packed_array_le #(parameter depth = 2, localparam width = 2**depth) (
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input [width-1:0] in, input [depth-1:0] shift, output [width-1:0]out);
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localparam offset = -2;
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/*verilator lint_off LITENDIAN*/
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reg [offset:depth+offset][offset:width-1+offset] tmp; /*verilator split_var*/
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/*verilator lint_on LITENDIAN*/
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generate
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for(genvar i = 0; i < depth; ++i) begin
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always_comb
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/*verilator lint_off ALWCOMBORDER*/
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if (shift[i]) begin
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tmp[i+1+offset] = {tmp[i+offset][width-(2**i)+offset:width-1+offset], tmp[i+offset][offset:width-(2**i)-1+offset]};
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end else begin // actulally just tmp[i+1+offset] = tmp[i+offset]
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tmp[i+1+offset][0+offset:2+offset] = tmp[i+offset][0+offset:2+offset];
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tmp[i+1+offset][3+offset] = tmp[i+offset][3+offset];
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{tmp[i+1+offset][4+offset],tmp[i+1+offset][5+offset]} = {tmp[i+offset][4+offset], tmp[i+offset][5+offset]};
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{tmp[i+1+offset][7+offset],tmp[i+1+offset][6+offset]} = {tmp[i+offset][7+offset], tmp[i+offset][6+offset]};
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end
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/*verilator lint_on ALWCOMBORDER*/
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end
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endgenerate
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assign tmp[0+offset] = in;
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assign out = tmp[depth+offset];
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endmodule
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module barshift_1d_packed_struct #(localparam depth = 3, localparam width = 2**depth) (
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input [width-1:0] in, input [depth-1:0] shift, output [width-1:0]out);
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typedef struct packed {
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logic [width-1:0] v0, v1, v2, v3;
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} data_type;
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wire data_type tmp; /*verilator split_var*/
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assign tmp.v0 = in;
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assign tmp.v1 = shift[0] == 1'b1 ? {tmp.v0[(1 << 0)-1:0], tmp.v0[width-1:2**0]} : tmp.v0;
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assign tmp.v2 = shift[1] == 1'b1 ? {tmp.v1[(1 << 1)-1:0], tmp.v1[width-1:2**1]} : tmp.v1;
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assign tmp.v3 = shift[2] == 1'b1 ? {tmp.v2[(1 << 2)-1:0], tmp.v2[width-1:2**2]} : tmp.v2;
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assign out = tmp.v3;
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endmodule
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module barshift_bitslice #(parameter depth = 2, localparam width = 2**depth) (
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input [width-1:0] in, input [depth-1:0] shift, output [width-1:0]out);
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/*verilator lint_off LITENDIAN*/
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wire [0:width*(depth+1) - 1] tmp; /*verilator split_var*/
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/*verilator lint_on LITENDIAN*/
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generate
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for(genvar i = 0; i < depth; ++i) begin
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always_comb
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if (shift[i]) begin
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tmp[width*(i+1):width*(i+1+1)-1] = {tmp[width*(i+1)-(1<<i):width*(i+1)-1], tmp[width*i:width*i+((width-1) - (2**i))]};
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end else begin
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tmp[width*(i+1):width*(i+1+1)-1] = tmp[width*i:width*(i+1)-1];
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end
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end
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endgenerate
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assign tmp[width*0:width*(0+1)-1] = in;
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assign out = tmp[width*depth:width*(depth+1)-1];
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endmodule
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module t(/*AUTOARG*/ clk);
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input clk;
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localparam depth = 3;
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localparam width = 2**depth;
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logic [width-1:0] in, out0;
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logic [depth-1:0] shift = 0;
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input clk;
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localparam depth = 3;
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localparam width = 2**depth;
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localparam numsub = 7;
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logic [width-1:0] in;
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logic [width-1:0] out[0:numsub-1];
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logic [depth-1:0] shift = 0;
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`ifndef VERILATOR
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// The following variables can not be splitted. will see warnings.
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logic should_show_warning0; /*verilator split_var*/
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logic [1:0][7:0]should_show_warning1; /*verilator split_var*/
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logic [7:0]should_show_warning2[0:1][0:3]; /*verilator split_var*/
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`endif
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// barrel shifter
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barshift_1d_unpacked #(.depth(depth)) shifter0(.in(in), .out(out[0]), .shift(shift));
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barshift_1d_unpacked_struct0 #(.depth(depth)) shifter1(.in(in), .out(out[1]), .shift(shift));
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barshift_1d_unpacked_struct1 #(.depth(depth)) shifter2(.in(in), .out(out[2]), .shift(shift));
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barshift_2d_packed_array #(.depth(depth)) shifter3(.in(in), .out(out[3]), .shift(shift));
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barshift_2d_packed_array_le #(.depth(depth)) shifter4(.in(in), .out(out[4]), .shift(shift));
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barshift_1d_packed_struct shifter5(.in(in), .out(out[5]), .shift(shift));
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barshift_bitslice #(.depth(depth)) shifter6(.in(in), .out(out[6]), .shift(shift));
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// barrel shifter
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barshift #(.depth(depth)) shifter0(.in(in), .out(out0), .shift(shift));
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assign in = 8'b10001110;
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logic [7:0] [7:0] exp = {
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8'b10001110, 8'b01000111, 8'b10100011, 8'b11010001,
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8'b11101000, 8'b01110100, 8'b00111010, 8'b00011101};
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always @(posedge clk) begin
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$display("in:%b shift:%d out:%b exp:%b", in, shift, out0, exp[7-shift]);
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if (out0 != exp[7-shift]) $stop;
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if (shift == 7) begin
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$write("*-* All Finished *-*\n");
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$finish;
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assign in = 8'b10001110;
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/*verilator lint_off LITENDIAN*/
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logic [7:0] [7:0] exp = {
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8'b10001110, 8'b01000111, 8'b10100011, 8'b11010001,
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8'b11101000, 8'b01110100, 8'b00111010, 8'b00011101};
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/*verilator lint_on LITENDIAN*/
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always @(posedge clk) begin
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automatic bit failed = 0;
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$display("in:%b shift:%d exp:%b", in, shift, exp[7-shift]);
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for (int i = 0; i < numsub; ++i) begin
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if (out[i] != exp[7-shift]) begin
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$display("Missmatch out[%d]:%b", i, out[i]);
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failed = 1;
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end
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end
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if (failed) $stop;
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if (shift == 7) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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shift <= shift + 1;
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end
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shift <= shift + 1;
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end
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endmodule
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@ -1,22 +1,34 @@
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%Warning-SPLITVAR: t/t_split_var_1_bad.v:4: Stray pragma of split_var is detected.
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%Warning-SPLITVAR: t/t_split_var_1_bad.v:2: Stray pragma of split_var is detected.
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: ... In instance t
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/*verilator split_var*/
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^~~~~~~~~~~~~~~~~~~~~~~
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/*verilator split_var*/
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^~~~~~~~~~~~~~~~~~~~~~~
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... Use "/* verilator lint_off SPLITVAR */" and lint_on around source to disable this message.
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%Warning-SPLITVAR: t/t_split_var_1_bad.v:7: Pragma split_var is specified on 'should_show_warning0' which type is not supported yet. Only unpacked 1D array is supported by this version.
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: ... In instance t
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logic should_show_warning0; /*verilator split_var*/
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^~~~~~~~~~~~~~~~~~~~~~~
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%Warning-SPLITVAR: t/t_split_var_1_bad.v:8: Pragma split_var is specified on 'should_show_warning1' which type is not supported yet. Only unpacked 1D array is supported by this version.
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: ... In instance t
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logic [1:0][7:0]should_show_warning1; /*verilator split_var*/
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^~~~~~~~~~~~~~~~~~~~~~~
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%Warning-SPLITVAR: t/t_split_var_1_bad.v:9: Pragma split_var is specified on 'should_show_warning2' which type is not supported yet. Only unpacked 1D array is supported by this version.
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: ... In instance t
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wire [7:0]should_show_warning2[0:1][0:3]; /*verilator split_var*/
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^~~~~~~~~~~~~~~~~~~~~~~
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%Warning-SPLITVAR: t/t_split_var_1_bad.v:30: Variable 'cannot_split' will not be split because index cannot be determined statically.
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: ... In instance t.i_sub0
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rd_data = cannot_split[addr];
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^~~~
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rd_data = cannot_split[addr];
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^~~~
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%Warning-SPLITVAR: t/t_split_var_1_bad.v:39: Variable 'cannot_split0' will not be split because the entire unpacked array is referred. Such access is not supported yet.
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: ... In instance t.i_sub1
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cannot_split1 = cannot_split0;
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^~~~~~~~~~~~~
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%Warning-SPLITVAR: t/t_split_var_1_bad.v:39: Variable 'cannot_split1' will not be split because the entire unpacked array is referred. Such access is not supported yet.
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: ... In instance t.i_sub1
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cannot_split1 = cannot_split0;
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^~~~~~~~~~~~~
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%Warning-SPLITVAR: t/t_split_var_1_bad.v:5: Pragma split_var is specified on a variable whose type is not supported. Unpacked dimension must be 1D or none and packed portion must be an aggregate type of bit or logic.
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: ... In instance t
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real should_show_warning0; /*verilator split_var*/
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^~~~~~~~~~~~~~~~~~~~~~~
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%Warning-SPLITVAR: t/t_split_var_1_bad.v:6: Pragma split_var is specified on a variable whose type is not supported. Unpacked dimension must be 1D or none and packed portion must be an aggregate type of bit or logic.
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: ... In instance t
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string should_show_warning1[0:2]; /*verilator split_var*/
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^~~~~~~~~~~~~~~~~~~~
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%Warning-SPLITVAR: t/t_split_var_1_bad.v:7: Pragma split_var is specified on a variable whose type is not supported. Unpacked dimension must be 1D or none and packed portion must be an aggregate type of bit or logic.
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: ... In instance t
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wire [7:0]should_show_warning2[0:1][0:3]; /*verilator split_var*/
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^~~~~~~~~~~~~~~~~~~~~~~
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%Warning-SPLITVAR: t/t_split_var_1_bad.v:50: Variable 'cannot_split' will not be split because bit range cannot be determined statically.
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: ... In instance t.i_sub2
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rd_data = cannot_split[addr];
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^
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%Error: Exiting due to
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@ -1,32 +1,52 @@
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module t();
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/*stray pragma */ /*verilator split_var*/
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/*stray pragma */ /*verilator split_var*/
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// The following variables can not be splitted. will see warnings.
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logic should_show_warning0; /*verilator split_var*/
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logic [1:0][7:0]should_show_warning1; /*verilator split_var*/
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wire [7:0]should_show_warning2[0:1][0:3]; /*verilator split_var*/
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// The following variables can not be splitted. will see warnings.
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real should_show_warning0; /*verilator split_var*/
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string should_show_warning1[0:2]; /*verilator split_var*/
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wire [7:0]should_show_warning2[0:1][0:3]; /*verilator split_var*/
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logic [3:0] addr;
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logic [7:0] rd_data;
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logic [3:0] addr;
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logic [7:0] rd_data0, rd_data1, rd_data2;
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sub0 i_sub0(.addr(addr), .rd_data(rd_data));
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sub0 i_sub0(.addr(addr), .rd_data(rd_data0));
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sub1 i_sub1( .rd_data(rd_data1));
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sub2 i_sub2(.addr(addr), .rd_data(rd_data2));
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initial begin
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addr = 0;
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addr = 1;
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$finish;
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end
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initial begin
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addr = 0;
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addr = 1;
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$finish;
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end
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endmodule
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module sub0(input [3:0]addr, output logic [7:0] rd_data);
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logic [7:0] cannot_split[0:15]; /*verilator split_var*/
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always_comb
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rd_data = cannot_split[addr];
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logic [7:0] cannot_split[0:15]; /*verilator split_var*/
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always_comb
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rd_data = cannot_split[addr];
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endmodule
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module sub1(output logic [7:0] rd_data);
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logic [7:0] cannot_split0[0:15]; /*verilator split_var*/
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logic [7:0] cannot_split1[0:15]; /*verilator split_var*/
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always_comb begin
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cannot_split1 = cannot_split0;
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rd_data = cannot_split1[0];
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end
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endmodule
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module sub2(input [3:0]addr, output logic [7:0] rd_data);
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logic [15:0] [7:0] cannot_split; /*verilator split_var*/
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always_comb
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rd_data = cannot_split[addr];
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endmodule
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