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Fix conditional assignments of slices where conditional is an array, bug215

This commit is contained in:
Wilson Snyder 2010-02-01 06:52:48 -05:00
parent 46dbc7157d
commit a41aefe77d
2 changed files with 18 additions and 4 deletions
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14
src/V3Slice.cpp
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@ -56,7 +56,7 @@ class SliceCloneVisitor : public AstNVisitor {
// STATE
vector<vector<unsigned> > m_selBits; // Indexes of the ArraySel we are expanding
unsigned m_vecIdx; // Current vector index
int m_vecIdx; // Current vector index
unsigned m_depth; // Number of ArraySel's from the VarRef
AstVarRef* m_refp; // VarRef under this ArraySel
@ -73,7 +73,7 @@ class SliceCloneVisitor : public AstNVisitor {
// This is the top of an ArraySel, setup
m_refp = nodep->user1p()->castNode()->castVarRef();
m_vecIdx += 1;
if (m_vecIdx == m_selBits.size()) {
if (m_vecIdx == (int)m_selBits.size()) {
m_selBits.push_back(vector<unsigned>());
AstVar* varp = m_refp->varp();
int dimensions = varp->dimensions();
@ -174,7 +174,7 @@ class SliceVisitor : public AstNVisitor {
if (fromp) ++dim;
}
} while (fromp && selp);
if (!m_assignp->user1p()) nodep->v3fatalSrc("Couldn't find VarRef under the ArraySel");
if (!nodep->user1p()) nodep->v3fatalSrc("Couldn't find VarRef under the ArraySel");
return dim;
}
@ -232,7 +232,7 @@ class SliceVisitor : public AstNVisitor {
if (dimensions > 0) {
AstNode* newp = insertImplicit(nodep->cloneTree(false), 1, dimensions);
nodep->replaceWith(newp); nodep = NULL;
newp->iterateChildren(*this);
newp->accept(*this);
}
}
}
@ -278,6 +278,12 @@ class SliceVisitor : public AstNVisitor {
nodep->iterateChildren(*this);
}
virtual void visit(AstNodeCond* nodep, AstNUser*) {
// The conditional must be a single bit so only look at the expressions
nodep->expr1p()->accept(*this);
nodep->expr2p()->accept(*this);
}
// Return the first AstVarRef under the node
AstVarRef* findVarRefRecurse(AstNode* nodep) {
AstVarRef* refp = nodep->castVarRef();

8
test_regress/t/t_mem_slice.v
View File

@ -23,6 +23,11 @@ module t (/*AUTOARG*/
logic [1:0] command_A3 [1:0][2:0][3:0];
logic [1:0] command_B3 [1:0][2:0][3:0];
logic [2:0] use_A4nB4;
logic [8:0][1:0] active_command4;
logic [8:0][1:0] command_A4;
logic [8:0][1:0] command_B4;
logic [8:0] pipe1 [7:0];
logic [8:0] pipe1_input;
@ -32,6 +37,9 @@ module t (/*AUTOARG*/
assign active_command2 = (use_AnB) ? command_A2 : command_B2;
assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][2:0][3:0];
// Check we can cope with things other than packed arrays
assign active_command4 = (use_A4nB4[0]) ? command_A4 : command_B4;
always @ (posedge clk) begin
pipe1_input <= pipe1_input + 1;
pipe1[0] <= pipe1_input;