Fix error on case statement with all duplicate items, bug99.

Changes

@@ -7,6 +7,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Support decimal constants of arbitrary widths. [Mark Marshall]
 
+**** Fix error on case statement with all duplicate items, bug99. [Mark Marshall]
+
 **** Fix segfault on unrolling for's with bad inits, bug90. [Andreas Olofsson]
 
 **** Fix tristates causing "Assigned pin is neither...". [by Lane Brooks]

src/V3Case.cpp

@@ -219,6 +219,7 @@ private:
 	if (msb<0) {
 	    // There's no space for a IF.  We know upperValue is thus down to a specific
 	    // exact value, so just return the tree value
+	    // Note can't clone here, as we're going to check for equivelence above
 	    return m_valueItem[upperValue];
 	}
 	else {
@@ -284,6 +285,8 @@ private:
 
 	AstNode::user3ClearTree();
 	AstNode* ifrootp = replaceCaseFastRecurse(cexprp, m_caseWidth-1, 0UL);
+	// Case expressions can't be linked twice, so clone them
+	if (ifrootp && !ifrootp->user3()) ifrootp = ifrootp->cloneTree(true);
 
 	if (ifrootp) nodep->replaceWith(ifrootp);
 	else nodep->unlinkFrBack();

test_regress/t/t_case_dupitems.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_case_dupitems.v

@@ -0,0 +1,81 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2008 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer 	cyc=0;
+   reg [63:0] 	crc;
+   reg [63:0] 	sum;
+
+   // Take CRC data and apply to testblock inputs
+   wire [1:0]  in = crc[1:0];
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [1:0]		out;			// From test of Test.v
+   // End of automatics
+
+   Test test (/*AUTOINST*/
+	      // Outputs
+	      .out			(out[1:0]),
+	      // Inputs
+	      .in			(in[1:0]));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = {62'h0, out};
+
+   // What checksum will we end up with
+`define EXPECTED_SUM 64'hbb2d9709592f64bd
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+	 // Setup
+	 crc <= 64'h5aef0c8d_d70a4497;
+      end
+      else if (cyc<10) begin
+	 sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 if (sum !== `EXPECTED_SUM) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+endmodule
+
+module Test (/*AUTOARG*/
+   // Outputs
+   out,
+   // Inputs
+   in
+   );
+   input [1:0] in;
+   output reg [1:0] out;
+   always @* begin
+      // bug99: Internal Error: ../V3Ast.cpp:495: New node already linked?
+      case (in[1:0]) 
+	2'd0, 2'd1, 2'd2, 2'd3: begin
+	   out = in;
+	end
+      endcase
+   end
+endmodule
+