Fix monitor block sensitivity items (#4400) (#5294)

docs/CONTRIBUTORS

@@ -200,6 +200,7 @@ Tudor Timi
 Tymoteusz Blazejczyk
 Udi Finkelstein
 Unai Martinez-Corral
+Udaya Raj Subedi
 Valentin Atepalikhin
 Varun Koyyalagunta
 Vassilis Papaefstathiou

src/V3Assert.cpp

@@ -505,6 +505,22 @@ class AssertVisitor final : public VNVisitor {
         } else if (nodep->displayType() == VDisplayType::DT_MONITOR) {
             nodep->displayType(VDisplayType::DT_DISPLAY);
             const auto fl = nodep->fileline();
+            AstNode* monExprsp = nodep->fmtp()->exprsp();
+            AstSenItem* monSenItemsp = nullptr;
+            while (monExprsp) {
+                if (AstNodeVarRef* varrefp = VN_CAST(monExprsp, NodeVarRef)) {
+                    AstSenItem* const senItemp
+                        = new AstSenItem(fl, VEdgeType::ET_CHANGED,
+                                         new AstVarRef{fl, varrefp->varp(), VAccess::READ});
+                    if (!monSenItemsp) {
+                        monSenItemsp = senItemp;
+                    } else {
+                        monSenItemsp->addNext(senItemp);
+                    }
+                }
+                monExprsp = monExprsp->nextp();
+            }
+            AstSenTree* const monSenTree = new AstSenTree{fl, monSenItemsp};
             const auto monNum = ++m_monitorNum;
             // Where $monitor was we do "__VmonitorNum = N;"
             const auto newsetp = new AstAssign{fl, newMonitorNumVarRefp(nodep, VAccess::WRITE),
@@ -520,7 +536,7 @@ class AssertVisitor final : public VNVisitor {
                 stmtsp};
             ifp->isBoundsCheck(true);  // To avoid LATCH warning
             ifp->branchPred(VBranchPred::BP_UNLIKELY);
-            AstNode* const newp = new AstAlways{fl, VAlwaysKwd::ALWAYS, nullptr, ifp};
+            AstNode* const newp = new AstAlways{fl, VAlwaysKwd::ALWAYS, monSenTree, ifp};
             m_modp->addStmtsp(newp);
         } else if (nodep->displayType() == VDisplayType::DT_STROBE) {
             nodep->displayType(VDisplayType::DT_DISPLAY);

test_regress/t/t_sys_delta_monitor.out

@@ -0,0 +1,14 @@
+[0] monitor0 00000004
+[1] monitor0 00000005
+[2] monitor0 00000009
+[3] monitor0 0000000a
+[4] monitor0 0000000e
+[5] monitor0 0000000f
+[6] monitor0 00000013
+[7] monitor0 00000014
+[8] monitor0 00000018
+[9] monitor0 00000019
+[10] monitor0 0000001d
+[11] monitor0 0000001e
+[12] monitor0 00000022
+*-* All Finished *-*

test_regress/t/t_sys_delta_monitor.pl

@@ -0,0 +1,24 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+	verilator_flags2 => ["--exe --main --timing --timescale 1ns/1ns"],
+    );
+
+execute(
+    check_finished => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+
+1;

test_regress/t/t_sys_delta_monitor.v

@@ -0,0 +1,24 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+module t(/*AUTOARG*/);
+logic [31:0] tmp;
+logic [31:0] tmp2;
+logic [31:0] tmp3;
+initial begin
+    tmp = 0;
+    $monitor("[%0t] monitor0 %h", $time, tmp);
+    while (tmp < 32) begin
+        tmp = tmp + 1;
+        if ((tmp % 5) == 1) begin
+            tmp = tmp + 2;
+            tmp = tmp + 1;
+        end
+		#1;
+    end
+    $write("*-* All Finished *-*\n");
+    $finish();
+end
+endmodule

test_regress/t/t_sys_monitor.out

@@ -17,4 +17,3 @@
 [290] cyc=29 new-monitor
 [300] cyc=30 new-monitor
 *-* All Finished *-*
-[310] cyc=31 new-monitor

test_regress/t/t_sys_monitor.v

@@ -38,6 +38,7 @@ module t(/*AUTOARG*/
          $monitoron;
       end
       else if (cyc == 30) begin
+      	 $monitoroff;  // To avoid inconsistent output between --vlt and --vltmt
          $write("*-* All Finished *-*\n");
          $finish;
       end