Add verilator lint_save/lint_restore

git-svn-id: file://localhost/svn/verilator/trunk/verilator@912 77ca24e4-aefa-0310-84f0-b9a241c72d87

Changes

@@ -7,6 +7,9 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **   Add --lint-only option.
 
+***  Add /*verilator lint_save*/ and /*verilator lint_restore*/ to allow
+     friendly control over re-enabling lint messages. [Gerald Williams]
+
 ***  Support SystemVerilog .name and .* interconnect.
 
 ***  Support while and do-while loops.

bin/verilator

@@ -1152,6 +1152,26 @@ Disable the specified warning message for any warnings following the comment.
 
 Re-enable the specified warning message for any warnings following the comment.
 
+=item /*verilator lint_restore*/
+
+After a /*verilator lint_save*/, pop the stack containing lint message
+state.  Often this is useful at the bottom of include files.
+
+=item /*verilator lint_save*/
+
+Push the current state of what lint messages are turned on or turned off to
+a stack.  Later meta-comments may then lint_on or lint_off specific
+messages, then return to the earlier message state by using /*verilator
+lint_restore*/.  For example:
+
+    // verilator lint_save
+    // verilator lint_off SOME_WARNING
+    ...  // code needing SOME_WARNING turned off
+    // verilator lint_restore
+
+If SOME_WARNING was on before the lint_off, it will now be restored to on,
+and if it was off before the lint_off it will remain off.
+
 =item /*verilator no_inline_task*/ 
 
 Used in a function or task variable definition section to specify the

src/V3Error.h

@@ -198,7 +198,8 @@ public:
     void warnOff(V3ErrorCode code, bool flag) { m_warnOff.set(code,flag); }	// Turn on/off warning messages on this line.
     bool warnOff(const string& code, bool flag);  // Returns 1 if ok
     bool warnIsOff(V3ErrorCode code);
-    void warnResetDefault() { m_warnOff=s_defaultFileLine.m_warnOff; }
+    void warnStateFrom(const FileLine& from) { m_warnOff=from.m_warnOff; }
+    void warnResetDefault() { warnStateFrom(s_defaultFileLine); }
 
     void	v3errorEnd(ostringstream& str);
     inline bool operator==(FileLine rhs) { return (m_lineno==rhs.m_lineno && m_filename==rhs.m_filename); }

src/V3Read.h

@@ -43,6 +43,7 @@ class V3Read {
     int		m_lastVerilogState;	// Last LEX state in `begin_keywords
     deque<string*> m_stringps;		// Created strings for later cleanup
     deque<V3Number*> m_numberps;	// Created numbers for later cleanup
+    deque<FileLine>  m_lintState;	// Current lint state for save/restore
     //int debug() { return 9; }
 
 protected:
@@ -55,6 +56,8 @@ protected:
     static void ppline (const char* text);
     static void incLineno() { s_readp->fileline()->incLineno(); }
     static void verilatorCmtLint(const char* text, bool on);
+    static void verilatorCmtLintSave();
+    static void verilatorCmtLintRestore();
     static void verilatorCmtBad(const char* text);
     static void pushBeginKeywords(int state) { s_readp->m_inBeginKwd++; s_readp->m_lastVerilogState=state; }
     static bool popBeginKeywords() { if (s_readp->m_inBeginKwd) { s_readp->m_inBeginKwd--; return true; } else return false; }

src/verilog.l

@@ -54,6 +54,19 @@ void V3Read::verilatorCmtLint(const char* textp, bool warnOff) {
 	yyerrorf("Unknown verilator lint message code: %s, in %s",msg.c_str(), textp);
     }
 }
+
+void V3Read::verilatorCmtLintSave() {
+    s_readp->m_lintState.push_back(*V3Read::fileline());
+}
+void V3Read::verilatorCmtLintRestore() {
+    if (s_readp->m_lintState.empty()) {
+	yyerror("/*verilator lint_restore*/ without matching save.");
+	return;
+    }
+    V3Read::fileline()->warnStateFrom(s_readp->m_lintState.back());
+    s_readp->m_lintState.pop_back();
+}
+
 void V3Read::verilatorCmtBad(const char* textp) {
     yyerrorf("Unknown verilator comment: %s",textp);
 }
@@ -515,6 +528,7 @@ escid	\\[^ \t\f\r\n]+
   "/*verilator coverage_block_off*/"	{yylval.fileline = CRELINE(); return yVL_COVER_OFF;}
   "/*verilator full_case*/"		{yylval.fileline = CRELINE(); return yVL_FULL_CASE;}
   "/*verilator inline_module*/"		{yylval.fileline = CRELINE(); return yVL_INLINE_MODULE;}
+  "/*verilator isolate_assignments*/"	{yylval.fileline = CRELINE(); return yVL_ISOLATE_ASSIGNMENTS;}
   "/*verilator no_inline_module*/"	{yylval.fileline = CRELINE(); return yVL_NO_INLINE_MODULE;}
   "/*verilator no_inline_task*/"	{yylval.fileline = CRELINE(); return yVL_NO_INLINE_TASK;}
   "/*verilator parallel_case*/"		{yylval.fileline = CRELINE(); return yVL_PARALLEL_CASE;}
@@ -522,12 +536,13 @@ escid	\\[^ \t\f\r\n]+
   "/*verilator public_flat*/"		{yylval.fileline = CRELINE(); return yVL_PUBLIC_FLAT;}
   "/*verilator public_module*/"		{yylval.fileline = CRELINE(); return yVL_PUBLIC_MODULE;}
   "/*verilator sc_clock*/"		{yylval.fileline = CRELINE(); return yVL_CLOCK;}
-  "/*verilator isolate_assignments*/"	{yylval.fileline = CRELINE(); return yVL_ISOLATE_ASSIGNMENTS;}
   "/*verilator systemc_clock*/"		{yylval.fileline = CRELINE(); return yVL_CLOCK;}
   "/*verilator tracing_off*/"		{yylval.fileline = CRELINE(); return yVL_TRACING_OFF;}
   "/*verilator tracing_on*/"		{yylval.fileline = CRELINE(); return yVL_TRACING_ON;}
   "/*verilator lint_off"[^*]*"*/"	{V3Read::verilatorCmtLint(yytext, true); }
   "/*verilator lint_on"[^*]*"*/"	{V3Read::verilatorCmtLint(yytext, false); }
+  "/*verilator lint_restore*/"		{V3Read::verilatorCmtLintRestore(); }
+  "/*verilator lint_save*/"		{V3Read::verilatorCmtLintSave(); }
 
   "/*"[^*]*"*/"				{V3Read::verilatorCmtBad(yytext); }
 }

test_regress/t/t_lint_restore_bad.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 v_flags2 => ["--lint-only"],
+	 fails=>1,
+	 expect=>
+'.*%Warning-WIDTH: t/t_lint_restore_bad.v:\d+: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST generates 64 bits.
+%Warning-WIDTH: Use .*
+%Error: Exiting due to.*',
+	 ) if $Last_Self->{v3};
+
+ok(1);
+1;

test_regress/t/t_lint_restore_bad.v

@@ -0,0 +1,23 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t ();
+
+   reg [3:0] four;
+   reg [4:0] five;
+
+   // verilator lint_save
+
+   // verilator lint_off WIDTH
+   initial four = 64'h1;
+
+   // verilator lint_restore
+
+   initial five = 64'h1;
+
+   initial $stop;
+
+endmodule