mirror of
https://github.com/verilator/verilator.git
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+7
-1
@@ -127,6 +127,7 @@ private:
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// STATE
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VDouble0 m_statCaseFast; // Statistic tracking
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VDouble0 m_statCaseSlow; // Statistic tracking
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AstNode* m_alwaysp = nullptr; // Always in which case is located
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// Per-CASE
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int m_caseWidth = 0; // Width of valueItems
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@@ -475,12 +476,17 @@ private:
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++m_statCaseFast;
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VL_DO_DANGLING(replaceCaseFast(nodep), nodep);
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} else {
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// If a case statement is whole, presume signals involved aren't forming a latch
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if (m_alwaysp) m_alwaysp->fileline()->warnOff(V3ErrorCode::LATCH, true);
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++m_statCaseSlow;
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VL_DO_DANGLING(replaceCaseComplicated(nodep), nodep);
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}
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}
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//--------------------
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virtual void visit(AstNode* nodep) override { iterateChildren(nodep); }
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virtual void visit(AstNode* nodep) override {
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if (VN_IS(nodep, Always)) { m_alwaysp = nodep; }
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iterateChildren(nodep);
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}
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public:
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// CONSTRUCTORS
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