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Fix JSON dump missing output ports (#6751) (#6831)

This commit is contained in:
Oleh Maksymenko 2025-12-19 14:30:33 +02:00 committed by GitHub
parent be08862109
commit a098e4894f
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
19 changed files with 334 additions and 56 deletions
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35
src/V3LinkLevel.cpp
View File

@ -414,3 +414,38 @@ void V3LinkLevel::wrapTopCell(AstNetlist* rootp) {
} }
} }
} }
void V3LinkLevel::nonWrapTop(AstNetlist* rootp) {
// Perform variable setting step for top modules to prevent
// optimizing away primary ports when only serializing input
if (!rootp->modulesp()) { // Later V3LinkDot will warn
UINFO(1, "No module found");
return;
}
// For all top modules
for (AstNodeModule* modp = rootp->modulesp(); modp && modp->isTop();
modp = VN_AS(modp->nextp(), NodeModule)) {
if (VN_IS(modp, Package)) continue;
UINFO(5, "LOOP " << modp);
for (AstNode* subnodep = modp->stmtsp(); subnodep; subnodep = subnodep->nextp()) {
if (AstVar* const varp = VN_CAST(subnodep, Var)) {
UINFO(8, "VARWRAP " << varp);
if (varp->isIO()) {
varp->protect(false);
varp->sigPublic(true);
varp->primaryIO(true);
if (varp->isRef() || varp->isConstRef()) {
varp->v3warn(E_UNSUPPORTED,
"Unsupported: ref/const ref as primary input/output: "
<< varp->prettyNameQ());
}
if (v3Global.opt.systemC()) varp->sc(true);
if (v3Global.opt.noTraceTop()) varp->trace(false);
}
}
}
}
}

1
src/V3LinkLevel.h
View File

@ -37,6 +37,7 @@ class V3LinkLevel final {
public: public:
static void modSortByLevel() VL_MT_DISABLED; static void modSortByLevel() VL_MT_DISABLED;
static void wrapTop(AstNetlist* rootp) VL_MT_DISABLED; static void wrapTop(AstNetlist* rootp) VL_MT_DISABLED;
static void nonWrapTop(AstNetlist* rootp) VL_MT_DISABLED;
}; };
#endif // Guard #endif // Guard

2
src/Verilator.cpp
View File

@ -251,6 +251,8 @@ static void process() {
// Move packages to under new top // Move packages to under new top
// Must do this after we know parameters and dtypes (as don't clone dtype decls) // Must do this after we know parameters and dtypes (as don't clone dtype decls)
V3LinkLevel::wrapTop(v3Global.rootp()); V3LinkLevel::wrapTop(v3Global.rootp());
} else {
V3LinkLevel::nonWrapTop(v3Global.rootp());
} }
// Propagate constants into expressions // Propagate constants into expressions

6
test_regress/t/t_json_only_first.out
View File

@ -2,9 +2,9 @@
"modulesp": [ "modulesp": [
{"type":"MODULE","name":"t","addr":"(E)","loc":"d,7:8,7:9","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"t","level":1,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], {"type":"MODULE","name":"t","addr":"(E)","loc":"d,7:8,7:9","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"t","level":1,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
"stmtsp": [ "stmtsp": [
{"type":"VAR","name":"q","addr":"(F)","loc":"d,15:22,15:23","dtypep":"(G)","origName":"q","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"q","addr":"(F)","loc":"d,15:22,15:23","dtypep":"(G)","origName":"q","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"clk","addr":"(H)","loc":"d,13:10,13:13","dtypep":"(I)","origName":"clk","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"clk","addr":"(H)","loc":"d,13:10,13:13","dtypep":"(I)","origName":"clk","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"d","addr":"(J)","loc":"d,14:16,14:17","dtypep":"(G)","origName":"d","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"d","addr":"(J)","loc":"d,14:16,14:17","dtypep":"(G)","origName":"d","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"between","addr":"(K)","loc":"d,17:22,17:29","dtypep":"(G)","origName":"between","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"between","addr":"(K)","loc":"d,17:22,17:29","dtypep":"(G)","origName":"between","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"VAR","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"CELL","name":"cell1","addr":"(L)","loc":"d,20:4,20:9","origName":"cell1","recursive":false,"modp":"(M)", {"type":"CELL","name":"cell1","addr":"(L)","loc":"d,20:4,20:9","origName":"cell1","recursive":false,"modp":"(M)",
"pinsp": [ "pinsp": [

2
test_regress/t/t_json_only_output.out
View File

@ -2,7 +2,7 @@
"modulesp": [ "modulesp": [
{"type":"MODULE","name":"m","addr":"(E)","loc":"d,7:8,7:9","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"m","level":1,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], {"type":"MODULE","name":"m","addr":"(E)","loc":"d,7:8,7:9","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"m","level":1,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
"stmtsp": [ "stmtsp": [
{"type":"VAR","name":"clk","addr":"(F)","loc":"d,8:10,8:13","dtypep":"(G)","origName":"clk","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} {"type":"VAR","name":"clk","addr":"(F)","loc":"d,8:10,8:13","dtypep":"(G)","origName":"clk","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}
]} ]}
],"filesp": [], ],"filesp": [],
"miscsp": [ "miscsp": [

72
test_regress/t/t_json_only_primary_io.out Normal file
View File

@ -0,0 +1,72 @@
{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED",
"modulesp": [
{"type":"MODULE","name":"top","addr":"(E)","loc":"d,7:8,7:11","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"top","level":1,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
"stmtsp": [
{"type":"VAR","name":"clk","addr":"(F)","loc":"d,8:9,8:12","dtypep":"(G)","origName":"clk","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"a1","addr":"(H)","loc":"d,9:9,9:11","dtypep":"(G)","origName":"a1","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"a2","addr":"(I)","loc":"d,10:9,10:11","dtypep":"(G)","origName":"a2","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"ready","addr":"(J)","loc":"d,11:10,11:15","dtypep":"(G)","origName":"ready","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"ready_reg","addr":"(K)","loc":"d,13:8,13:17","dtypep":"(G)","origName":"ready_reg","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"CELL","name":"and_cell","addr":"(L)","loc":"d,15:11,15:19","origName":"and_cell","recursive":false,"modp":"(M)",
"pinsp": [
{"type":"PIN","name":"a1","addr":"(N)","loc":"d,16:6,16:8","svDotName":true,"svImplicit":false,"modVarp":"(O)","modPTypep":"UNLINKED",
"exprp": [
{"type":"VARREF","name":"a1","addr":"(P)","loc":"d,16:9,16:11","dtypep":"(G)","access":"RD","varp":"(H)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"}
]},
{"type":"PIN","name":"a2","addr":"(Q)","loc":"d,17:6,17:8","svDotName":true,"svImplicit":false,"modVarp":"(R)","modPTypep":"UNLINKED",
"exprp": [
{"type":"VARREF","name":"a2","addr":"(S)","loc":"d,17:9,17:11","dtypep":"(G)","access":"RD","varp":"(I)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"}
]},
{"type":"PIN","name":"zn","addr":"(T)","loc":"d,18:6,18:8","svDotName":true,"svImplicit":false,"modVarp":"(U)","modPTypep":"UNLINKED",
"exprp": [
{"type":"VARREF","name":"ready_reg","addr":"(V)","loc":"d,18:9,18:18","dtypep":"(G)","access":"WR","varp":"(K)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"}
]}
],"paramsp": [],"rangep": [],"intfRefsp": []},
{"type":"ALWAYS","name":"","addr":"(W)","loc":"d,21:16,21:17","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [],
"stmtsp": [
{"type":"ASSIGNW","name":"","addr":"(X)","loc":"d,21:16,21:17","dtypep":"(G)",
"rhsp": [
{"type":"VARREF","name":"ready_reg","addr":"(Y)","loc":"d,13:8,13:17","dtypep":"(G)","access":"RD","varp":"(K)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"}
],
"lhsp": [
{"type":"VARREF","name":"ready","addr":"(Z)","loc":"d,21:16,21:17","dtypep":"(G)","access":"WR","varp":"(J)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
]}
]},
{"type":"MODULE","name":"and2_x1","addr":"(M)","loc":"d,24:8,24:15","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"and2_x1","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],
"stmtsp": [
{"type":"VAR","name":"a1","addr":"(O)","loc":"d,25:14,25:16","dtypep":"(G)","origName":"a1","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"a2","addr":"(R)","loc":"d,26:14,26:16","dtypep":"(G)","origName":"a2","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"zn","addr":"(U)","loc":"d,27:15,27:17","dtypep":"(G)","origName":"zn","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"ALWAYS","name":"","addr":"(AB)","loc":"d,29:15,29:16","keyword":"cont_assign","isSuspendable":false,"needProcess":false,"sentreep": [],
"stmtsp": [
{"type":"ASSIGNW","name":"","addr":"(BB)","loc":"d,29:15,29:16","dtypep":"(G)",
"rhsp": [
{"type":"AND","name":"","addr":"(CB)","loc":"d,29:21,29:22","dtypep":"(G)",
"lhsp": [
{"type":"VARREF","name":"a1","addr":"(DB)","loc":"d,25:14,25:16","dtypep":"(G)","access":"RD","varp":"(O)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"}
],
"rhsp": [
{"type":"VARREF","name":"a2","addr":"(EB)","loc":"d,26:14,26:16","dtypep":"(G)","access":"RD","varp":"(R)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"}
]}
],
"lhsp": [
{"type":"VARREF","name":"zn","addr":"(FB)","loc":"d,29:15,29:16","dtypep":"(G)","access":"WR","varp":"(U)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"}
],"timingControlp": [],"strengthSpecp": []}
]}
]}
],"filesp": [],
"miscsp": [
{"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(GB)",
"typesp": [
{"type":"BASICDTYPE","name":"logic","addr":"(G)","loc":"d,25:14,25:16","dtypep":"(G)","keyword":"logic","generic":true,"rangep": []},
{"type":"VOIDDTYPE","name":"","addr":"(GB)","loc":"a,0:0,0:0","dtypep":"(GB)","generic":false}
]},
{"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0",
"modulep": [
{"type":"MODULE","name":"@CONST-POOL@","addr":"(HB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
"stmtsp": [
{"type":"SCOPE","name":"@CONST-POOL@","addr":"(IB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(HB)","varsp": [],"blocksp": [],"inlinesp": []}
]}
]}
]}

23
test_regress/t/t_json_only_primary_io.py Executable file
View File

@ -0,0 +1,23 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
out_filename = test.obj_dir + "/V" + test.name + ".tree.json"
test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums'],
verilator_make_gmake=False,
make_top_shell=False,
make_main=False)
test.files_identical(out_filename, test.golden_filename)
test.passes()

30
test_regress/t/t_json_only_primary_io.v Normal file
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@ -0,0 +1,30 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module top(clk, a1, a2, ready);
input clk;
input a1;
input a2;
output ready;
wire ready_reg;
and2_x1 and_cell (
.a1(a1),
.a2(a2),
.zn(ready_reg)
);
assign ready = ready_reg;
endmodule
module and2_x1 (
input wire a1,
input wire a2,
output wire zn
);
assign zn = (a1 & a2);
endmodule

6
test_regress/t/t_json_only_tag.out
View File

@ -2,9 +2,9 @@
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"stmtsp": [ "stmtsp": [
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40
test_regress/t/t_var_port_json_only.out
View File

@ -2,68 +2,68 @@
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{"type":"VAR","name":"ref_var_logic_u6","addr":"(QB)","loc":"d,58:17,58:33","dtypep":"(RB)","origName":"ref_var_logic_u6","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"ref_var_logic_u6","addr":"(QB)","loc":"d,58:17,58:33","dtypep":"(RB)","origName":"ref_var_logic_u6","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []},
{"type":"VAR","name":"y_ref_var_logic","addr":"(SB)","loc":"d,58:41,58:56","dtypep":"(J)","origName":"y_ref_var_logic","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} {"type":"VAR","name":"y_ref_var_logic","addr":"(SB)","loc":"d,58:41,58:56","dtypep":"(J)","origName":"y_ref_var_logic","isSc":false,"isPrimaryIO":true,"isPrimaryClock":false,"direction":"REF","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}
]} ]}
],"filesp": [], ],"filesp": [],
"miscsp": [ "miscsp": [

2
test_regress/t/t_var_port_json_only.py
View File

@ -13,7 +13,7 @@ test.scenarios('vlt')
out_filename = test.obj_dir + "/V" + test.name + ".tree.json" out_filename = test.obj_dir + "/V" + test.name + ".tree.json"
test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums'], test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums', '--bbox-unsup'],
verilator_make_gmake=False, verilator_make_gmake=False,
make_top_shell=False, make_top_shell=False,
make_main=False) make_main=False)

40
test_regress/t/t_var_port_xml.out
View File

@ -57,54 +57,54 @@
</cells> </cells>
<netlist> <netlist>
<module loc="d,18,8,18,11" name="mh2" origName="mh2" topModule="1"> <module loc="d,18,8,18,11" name="mh2" origName="mh2" topModule="1">
<var loc="d,18,27,18,47" name="x_inout_wire_integer" dtype_id="1" dir="inout" pinIndex="1" vartype="integer" origName="x_inout_wire_integer"/> <var loc="d,18,27,18,47" name="x_inout_wire_integer" dtype_id="1" dir="inout" pinIndex="1" vartype="integer" origName="x_inout_wire_integer" public="true"/>
</module> </module>
<module loc="d,24,8,24,11" name="mh5" origName="mh5" topModule="1"> <module loc="d,24,8,24,11" name="mh5" origName="mh5" topModule="1">
<var loc="d,24,19,24,37" name="x_input_wire_logic" dtype_id="2" dir="input" pinIndex="1" vartype="logic" origName="x_input_wire_logic"/> <var loc="d,24,19,24,37" name="x_input_wire_logic" dtype_id="2" dir="input" pinIndex="1" vartype="logic" origName="x_input_wire_logic" public="true"/>
</module> </module>
<module loc="d,26,8,26,11" name="mh6" origName="mh6" topModule="1"> <module loc="d,26,8,26,11" name="mh6" origName="mh6" topModule="1">
<var loc="d,26,23,26,40" name="x_input_var_logic" dtype_id="2" dir="input" pinIndex="1" vartype="logic" origName="x_input_var_logic"/> <var loc="d,26,23,26,40" name="x_input_var_logic" dtype_id="2" dir="input" pinIndex="1" vartype="logic" origName="x_input_var_logic" public="true"/>
</module> </module>
<module loc="d,28,8,28,11" name="mh7" origName="mh7" topModule="1"> <module loc="d,28,8,28,11" name="mh7" origName="mh7" topModule="1">
<var loc="d,28,31,28,50" name="x_input_var_integer" dtype_id="1" dir="input" pinIndex="1" vartype="integer" origName="x_input_var_integer"/> <var loc="d,28,31,28,50" name="x_input_var_integer" dtype_id="1" dir="input" pinIndex="1" vartype="integer" origName="x_input_var_integer" public="true"/>
</module> </module>
<module loc="d,30,8,30,11" name="mh8" origName="mh8" topModule="1"> <module loc="d,30,8,30,11" name="mh8" origName="mh8" topModule="1">
<var loc="d,30,20,30,39" name="x_output_wire_logic" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="x_output_wire_logic"/> <var loc="d,30,20,30,39" name="x_output_wire_logic" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="x_output_wire_logic" public="true"/>
</module> </module>
<module loc="d,32,8,32,11" name="mh9" origName="mh9" topModule="1"> <module loc="d,32,8,32,11" name="mh9" origName="mh9" topModule="1">
<var loc="d,32,24,32,42" name="x_output_var_logic" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="x_output_var_logic"/> <var loc="d,32,24,32,42" name="x_output_var_logic" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="x_output_var_logic" public="true"/>
</module> </module>
<module loc="d,34,8,34,12" name="mh10" origName="mh10" topModule="1"> <module loc="d,34,8,34,12" name="mh10" origName="mh10" topModule="1">
<var loc="d,34,33,34,62" name="x_output_wire_logic_signed_p6" dtype_id="3" dir="output" pinIndex="1" vartype="logic" origName="x_output_wire_logic_signed_p6"/> <var loc="d,34,33,34,62" name="x_output_wire_logic_signed_p6" dtype_id="3" dir="output" pinIndex="1" vartype="logic" origName="x_output_wire_logic_signed_p6" public="true"/>
</module> </module>
<module loc="d,36,8,36,12" name="mh11" origName="mh11" topModule="1"> <module loc="d,36,8,36,12" name="mh11" origName="mh11" topModule="1">
<var loc="d,36,28,36,48" name="x_output_var_integer" dtype_id="1" dir="output" pinIndex="1" vartype="integer" origName="x_output_var_integer"/> <var loc="d,36,28,36,48" name="x_output_var_integer" dtype_id="1" dir="output" pinIndex="1" vartype="integer" origName="x_output_var_integer" public="true"/>
</module> </module>
<module loc="d,38,8,38,12" name="mh12" origName="mh12" topModule="1"> <module loc="d,38,8,38,12" name="mh12" origName="mh12" topModule="1">
<var loc="d,38,23,38,37" name="x_ref_logic_p6" dtype_id="4" dir="ref" pinIndex="1" vartype="logic" origName="x_ref_logic_p6"/> <var loc="d,38,23,38,37" name="x_ref_logic_p6" dtype_id="4" dir="ref" pinIndex="1" vartype="logic" origName="x_ref_logic_p6" public="true"/>
</module> </module>
<module loc="d,40,8,40,12" name="mh13" origName="mh13" topModule="1"> <module loc="d,40,8,40,12" name="mh13" origName="mh13" topModule="1">
<var loc="d,40,17,40,35" name="x_ref_var_logic_u6" dtype_id="5" dir="ref" pinIndex="1" vartype="port" origName="x_ref_var_logic_u6"/> <var loc="d,40,17,40,35" name="x_ref_var_logic_u6" dtype_id="5" dir="ref" pinIndex="1" vartype="port" origName="x_ref_var_logic_u6" public="true"/>
</module> </module>
<module loc="d,50,8,50,12" name="mh17" origName="mh17" topModule="1"> <module loc="d,50,8,50,12" name="mh17" origName="mh17" topModule="1">
<var loc="d,50,31,50,50" name="x_input_var_integer" dtype_id="1" dir="input" pinIndex="1" vartype="integer" origName="x_input_var_integer"/> <var loc="d,50,31,50,50" name="x_input_var_integer" dtype_id="1" dir="input" pinIndex="1" vartype="integer" origName="x_input_var_integer" public="true"/>
<var loc="d,50,57,50,75" name="y_input_wire_logic" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="y_input_wire_logic"/> <var loc="d,50,57,50,75" name="y_input_wire_logic" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="y_input_wire_logic" public="true"/>
</module> </module>
<module loc="d,52,8,52,12" name="mh18" origName="mh18" topModule="1"> <module loc="d,52,8,52,12" name="mh18" origName="mh18" topModule="1">
<var loc="d,52,24,52,42" name="x_output_var_logic" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="x_output_var_logic"/> <var loc="d,52,24,52,42" name="x_output_var_logic" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="x_output_var_logic" public="true"/>
<var loc="d,52,50,52,68" name="y_input_wire_logic" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="y_input_wire_logic"/> <var loc="d,52,50,52,68" name="y_input_wire_logic" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="y_input_wire_logic" public="true"/>
</module> </module>
<module loc="d,54,8,54,12" name="mh19" origName="mh19" topModule="1"> <module loc="d,54,8,54,12" name="mh19" origName="mh19" topModule="1">
<var loc="d,54,33,54,62" name="x_output_wire_logic_signed_p6" dtype_id="3" dir="output" pinIndex="1" vartype="logic" origName="x_output_wire_logic_signed_p6"/> <var loc="d,54,33,54,62" name="x_output_wire_logic_signed_p6" dtype_id="3" dir="output" pinIndex="1" vartype="logic" origName="x_output_wire_logic_signed_p6" public="true"/>
<var loc="d,54,72,54,92" name="y_output_var_integer" dtype_id="1" dir="output" pinIndex="2" vartype="integer" origName="y_output_var_integer"/> <var loc="d,54,72,54,92" name="y_output_var_integer" dtype_id="1" dir="output" pinIndex="2" vartype="integer" origName="y_output_var_integer" public="true"/>
</module> </module>
<module loc="d,56,8,56,12" name="mh20" origName="mh20" topModule="1"> <module loc="d,56,8,56,12" name="mh20" origName="mh20" topModule="1">
<var loc="d,56,23,56,41" name="x_ref_var_logic_p6" dtype_id="4" dir="ref" pinIndex="1" vartype="logic" origName="x_ref_var_logic_p6"/> <var loc="d,56,23,56,41" name="x_ref_var_logic_p6" dtype_id="4" dir="ref" pinIndex="1" vartype="logic" origName="x_ref_var_logic_p6" public="true"/>
<var loc="d,56,43,56,61" name="y_ref_var_logic_p6" dtype_id="4" dir="ref" pinIndex="2" vartype="logic" origName="y_ref_var_logic_p6"/> <var loc="d,56,43,56,61" name="y_ref_var_logic_p6" dtype_id="4" dir="ref" pinIndex="2" vartype="logic" origName="y_ref_var_logic_p6" public="true"/>
</module> </module>
<module loc="d,58,8,58,12" name="mh21" origName="mh21" topModule="1"> <module loc="d,58,8,58,12" name="mh21" origName="mh21" topModule="1">
<var loc="d,58,17,58,33" name="ref_var_logic_u6" dtype_id="6" dir="ref" pinIndex="1" vartype="port" origName="ref_var_logic_u6"/> <var loc="d,58,17,58,33" name="ref_var_logic_u6" dtype_id="6" dir="ref" pinIndex="1" vartype="port" origName="ref_var_logic_u6" public="true"/>
<var loc="d,58,41,58,56" name="y_ref_var_logic" dtype_id="2" dir="ref" pinIndex="2" vartype="logic" origName="y_ref_var_logic"/> <var loc="d,58,41,58,56" name="y_ref_var_logic" dtype_id="2" dir="ref" pinIndex="2" vartype="logic" origName="y_ref_var_logic" public="true"/>
</module> </module>
<typetable loc="a,0,0,0,0"> <typetable loc="a,0,0,0,0">
<unpackarraydtype loc="d,58,34,58,35" id="6" sub_dtype_id="2"> <unpackarraydtype loc="d,58,34,58,35" id="6" sub_dtype_id="2">

2
test_regress/t/t_var_port_xml.py
View File

@ -13,7 +13,7 @@ test.scenarios('vlt')
out_filename = test.obj_dir + "/V" + test.name + ".xml" out_filename = test.obj_dir + "/V" + test.name + ".xml"
test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only'], test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only', '--bbox-unsup'],
verilator_make_gmake=False, verilator_make_gmake=False,
make_top_shell=False, make_top_shell=False,
make_main=False) make_main=False)

6
test_regress/t/t_xml_first.out
View File

@ -18,9 +18,9 @@
</cells> </cells>
<netlist> <netlist>
<module loc="d,7,8,7,9" name="t" origName="t" topModule="1"> <module loc="d,7,8,7,9" name="t" origName="t" topModule="1">
<var loc="d,15,22,15,23" name="q" dtype_id="1" dir="output" pinIndex="1" vartype="logic" origName="q"/> <var loc="d,15,22,15,23" name="q" dtype_id="1" dir="output" pinIndex="1" vartype="logic" origName="q" public="true"/>
<var loc="d,13,10,13,13" name="clk" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="clk"/> <var loc="d,13,10,13,13" name="clk" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="clk" public="true"/>
<var loc="d,14,16,14,17" name="d" dtype_id="1" dir="input" pinIndex="3" vartype="logic" origName="d"/> <var loc="d,14,16,14,17" name="d" dtype_id="1" dir="input" pinIndex="3" vartype="logic" origName="d" public="true"/>
<var loc="d,17,22,17,29" name="between" dtype_id="1" vartype="logic" origName="between"/> <var loc="d,17,22,17,29" name="between" dtype_id="1" vartype="logic" origName="between"/>
<instance loc="d,20,4,20,9" name="cell1" defName="mod1__W4" origName="cell1"> <instance loc="d,20,4,20,9" name="cell1" defName="mod1__W4" origName="cell1">
<port loc="d,20,12,20,13" name="q" direction="out" portIndex="1"> <port loc="d,20,12,20,13" name="q" direction="out" portIndex="1">

2
test_regress/t/t_xml_output.out
View File

@ -15,7 +15,7 @@
</cells> </cells>
<netlist> <netlist>
<module loc="d,7,8,7,9" name="m" origName="m" topModule="1"> <module loc="d,7,8,7,9" name="m" origName="m" topModule="1">
<var loc="d,8,10,8,13" name="clk" tag="foo_op" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="clk"/> <var loc="d,8,10,8,13" name="clk" tag="foo_op" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="clk" public="true"/>
</module> </module>
<typetable loc="a,0,0,0,0"> <typetable loc="a,0,0,0,0">
<basicdtype loc="d,8,10,8,13" id="1" name="logic"/> <basicdtype loc="d,8,10,8,13" id="1" name="logic"/>

62
test_regress/t/t_xml_primary_io.out Normal file
View File

@ -0,0 +1,62 @@
<?xml version="1.0" ?>
<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml>
<files>
<file id="a" filename="&lt;built-in&gt;" language="1800-2023"/>
<file id="b" filename="&lt;command-line&gt;" language="1800-2023"/>
<file id="c" filename="input.vc" language="1800-2023"/>
<file id="d" filename="t/t_xml_primary_io.v" language="1800-2023"/>
</files>
<module_files>
<file id="d" filename="t/t_xml_primary_io.v" language="1800-2023"/>
</module_files>
<cells>
<cell loc="d,7,8,7,11" name="top" submodname="top" hier="top">
<cell loc="d,15,11,15,19" name="and_cell" submodname="and2_x1" hier="top.and_cell"/>
</cell>
</cells>
<netlist>
<module loc="d,7,8,7,11" name="top" origName="top" topModule="1">
<var loc="d,8,9,8,12" name="clk" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="clk" public="true"/>
<var loc="d,9,9,9,11" name="a1" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="a1" public="true"/>
<var loc="d,10,9,10,11" name="a2" dtype_id="1" dir="input" pinIndex="3" vartype="logic" origName="a2" public="true"/>
<var loc="d,11,10,11,15" name="ready" dtype_id="1" dir="output" pinIndex="4" vartype="logic" origName="ready" public="true"/>
<var loc="d,13,8,13,17" name="ready_reg" dtype_id="1" vartype="logic" origName="ready_reg"/>
<instance loc="d,15,11,15,19" name="and_cell" defName="and2_x1" origName="and_cell">
<port loc="d,16,6,16,8" name="a1" direction="in" portIndex="1">
<varref loc="d,16,9,16,11" name="a1" dtype_id="1"/>
</port>
<port loc="d,17,6,17,8" name="a2" direction="in" portIndex="2">
<varref loc="d,17,9,17,11" name="a2" dtype_id="1"/>
</port>
<port loc="d,18,6,18,8" name="zn" direction="out" portIndex="3">
<varref loc="d,18,9,18,18" name="ready_reg" dtype_id="1"/>
</port>
</instance>
<always loc="d,21,16,21,17">
<contassign loc="d,21,16,21,17" dtype_id="1">
<varref loc="d,13,8,13,17" name="ready_reg" dtype_id="1"/>
<varref loc="d,21,16,21,17" name="ready" dtype_id="1"/>
</contassign>
</always>
</module>
<module loc="d,24,8,24,15" name="and2_x1" origName="and2_x1">
<var loc="d,25,14,25,16" name="a1" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="a1"/>
<var loc="d,26,14,26,16" name="a2" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="a2"/>
<var loc="d,27,15,27,17" name="zn" dtype_id="1" dir="output" pinIndex="3" vartype="logic" origName="zn"/>
<always loc="d,29,15,29,16">
<contassign loc="d,29,15,29,16" dtype_id="1">
<and loc="d,29,21,29,22" dtype_id="1">
<varref loc="d,25,14,25,16" name="a1" dtype_id="1"/>
<varref loc="d,26,14,26,16" name="a2" dtype_id="1"/>
</and>
<varref loc="d,29,15,29,16" name="zn" dtype_id="1"/>
</contassign>
</always>
</module>
<typetable loc="a,0,0,0,0">
<basicdtype loc="d,25,14,25,16" id="1" name="logic"/>
<voiddtype loc="a,0,0,0,0" id="2"/>
</typetable>
</netlist>
</verilator_xml>

23
test_regress/t/t_xml_primary_io.py Executable file
View File

@ -0,0 +1,23 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
out_filename = test.obj_dir + "/V" + test.name + ".xml"
test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only'],
verilator_make_gmake=False,
make_top_shell=False,
make_main=False)
test.files_identical(out_filename, test.golden_filename)
test.passes()

30
test_regress/t/t_xml_primary_io.v Normal file
View File

@ -0,0 +1,30 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module top(clk, a1, a2, ready);
input clk;
input a1;
input a2;
output ready;
wire ready_reg;
and2_x1 and_cell (
.a1(a1),
.a2(a2),
.zn(ready_reg)
);
assign ready = ready_reg;
endmodule
module and2_x1 (
input wire a1,
input wire a2,
output wire zn
);
assign zn = (a1 & a2);
endmodule

6
test_regress/t/t_xml_tag.out
View File

@ -17,9 +17,9 @@
</cells> </cells>
<netlist> <netlist>
<module loc="d,12,8,12,9" name="m" origName="m" topModule="1"> <module loc="d,12,8,12,9" name="m" origName="m" topModule="1">
<var loc="d,14,11,14,17" name="clk_ip" tag="clk_ip" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="clk_ip"/> <var loc="d,14,11,14,17" name="clk_ip" tag="clk_ip" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="clk_ip" public="true"/>
<var loc="d,15,11,15,17" name="rst_ip" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="rst_ip"/> <var loc="d,15,11,15,17" name="rst_ip" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="rst_ip" public="true"/>
<var loc="d,16,11,16,17" name="foo_op" tag="foo_op" dtype_id="1" dir="output" pinIndex="3" vartype="logic" origName="foo_op"/> <var loc="d,16,11,16,17" name="foo_op" tag="foo_op" dtype_id="1" dir="output" pinIndex="3" vartype="logic" origName="foo_op" public="true"/>
<typedef loc="d,25,6,25,15" name="my_struct" tag="my_struct" dtype_id="2"/> <typedef loc="d,25,6,25,15" name="my_struct" tag="my_struct" dtype_id="2"/>
<instance loc="d,29,8,29,12" name="itop" defName="ifc" origName="itop"/> <instance loc="d,29,8,29,12" name="itop" defName="ifc" origName="itop"/>
<var loc="d,29,8,29,12" name="itop" dtype_id="3" vartype="ifaceref" origName="itop__Viftop"/> <var loc="d,29,8,29,12" name="itop" dtype_id="3" vartype="ifaceref" origName="itop__Viftop"/>