parent
54e637c72b
commit
a044697990
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@ -2128,9 +2128,11 @@ class WidthVisitor final : public VNVisitor {
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if (debug() >= 9) nodep->dumpTree("- CastPre: ");
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if (debug() >= 9) nodep->dumpTree("- CastPre: ");
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// if (debug()) nodep->backp()->dumpTree("- CastPreUpUp: ");
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// if (debug()) nodep->backp()->dumpTree("- CastPreUpUp: ");
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if (AstSigned* const fromp = VN_CAST(nodep->fromp(), Signed)) {
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if (AstSigned* const fromp = VN_CAST(nodep->fromp(), Signed)) {
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AstNode* const lhsp = fromp->lhsp()->unlinkFrBack();
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if (VN_IS(fromp->lhsp(), NodeStream)) {
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fromp->replaceWith(lhsp);
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AstNode* const lhsp = fromp->lhsp()->unlinkFrBack();
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VL_DO_DANGLING(fromp->deleteTree(), fromp);
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fromp->replaceWith(lhsp);
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VL_DO_DANGLING(fromp->deleteTree(), fromp);
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}
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}
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}
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userIterateAndNext(nodep->fromp(), WidthVP{SELF, PRELIM}.p());
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userIterateAndNext(nodep->fromp(), WidthVP{SELF, PRELIM}.p());
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if (debug() >= 9) nodep->dumpTree("- CastDit: ");
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if (debug() >= 9) nodep->dumpTree("- CastDit: ");
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios("simulator")
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test.compile()
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test.execute()
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test.passes()
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@ -0,0 +1,23 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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logic [7:0] smaller;
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logic [15:0] bigger;
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typedef logic [15:0] bigger_t;
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initial begin
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smaller = 8'hfa;
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bigger = bigger_t'(signed'(smaller));
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$display("%x", bigger); // NOCOMMIT
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if (bigger != 16'hfffa) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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