[#73220] update t_trace_saif test
This commit is contained in:
Mateusz Gancarz
parent
f25492df67
commit
9febcbb08d
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@ -1,141 +1,92 @@
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(SAIFILE
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(SAIFVERSION "2.0")
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(DIRECTION "backward")
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(DESIGN "t")
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(DESIGN "foo")
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(PROGRAM_NAME "Verilator")
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(VERSION "5.032")
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(DIVIDER / )
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(TIMESCALE 1ps)
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(DURATION 1000)
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(INSTANCE top
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(INSTANCE top
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(NET
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(clk (T0 505) (T1 495) (TX 0) (TC 199))
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(state\[0\] (T0 410) (T1 590) (TX 0) (TC 46))
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(state\[1\] (T0 540) (T1 460) (TX 0) (TC 45))
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(state\[2\] (T0 530) (T1 470) (TX 0) (TC 46))
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(state\[3\] (T0 540) (T1 460) (TX 0) (TC 44))
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(state\[4\] (T0 540) (T1 460) (TX 0) (TC 45))
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(clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199))
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(state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46))
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(state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
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(state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
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(state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44))
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(state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
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)
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(INSTANCE t
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(NET
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(clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199))
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(cyc\[0\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 100))
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(cyc\[1\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 50))
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(cyc\[2\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 25))
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(cyc\[3\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 12))
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(cyc\[4\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 6))
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(cyc\[5\] (T0 640) (T1 360) (TZ 0) (TX 0) (TB 0) (TC 3))
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(cyc\[6\] (T0 640) (T1 360) (TZ 0) (TX 0) (TB 0) (TC 1))
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(rstn (T0 110) (T1 890) (TZ 0) (TX 0) (TB 0) (TC 1))
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(state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46))
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(state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
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(state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
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(state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44))
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(state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
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(fst_parameter\[0\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
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(fst_parameter\[1\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
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(fst_parameter\[3\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
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(fst_parameter\[4\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
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(fst_parameter\[5\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
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(fst_parameter\[6\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
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(fst_lparam\[3\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
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(fst_lparam\[6\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
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(fst_lparam\[7\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
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(fst_lparam\[8\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
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(fst_supply1 (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
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(fst_tri1 (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
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)
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(INSTANCE test
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(NET
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(clk (T0 505) (T1 495) (TX 0) (TC 199))
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(cyc\[0\] (T0 500) (T1 500) (TX 0) (TC 100))
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(cyc\[1\] (T0 500) (T1 500) (TX 0) (TC 50))
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(cyc\[2\] (T0 520) (T1 480) (TX 0) (TC 25))
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(cyc\[3\] (T0 520) (T1 480) (TX 0) (TC 12))
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(cyc\[4\] (T0 520) (T1 480) (TX 0) (TC 6))
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(cyc\[5\] (T0 640) (T1 360) (TX 0) (TC 3))
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(cyc\[6\] (T0 640) (T1 360) (TX 0) (TC 1))
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(rstn (T0 110) (T1 890) (TX 0) (TC 1))
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(state\[0\] (T0 410) (T1 590) (TX 0) (TC 46))
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(state\[1\] (T0 540) (T1 460) (TX 0) (TC 45))
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(state\[2\] (T0 530) (T1 470) (TX 0) (TC 46))
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(state\[3\] (T0 540) (T1 460) (TX 0) (TC 44))
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(state\[4\] (T0 540) (T1 460) (TX 0) (TC 45))
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(fst_longint\[0\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[1\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[2\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[3\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[5\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[6\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[7\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[9\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[10\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[11\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[12\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[13\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[15\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[16\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[17\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[18\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[19\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[21\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[22\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[23\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[25\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[26\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[27\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[28\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[29\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[31\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[32\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[33\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[34\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[35\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[37\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[38\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[39\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[41\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[42\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[43\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[44\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[45\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[47\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[48\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[49\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[50\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[51\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[53\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[54\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[55\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[57\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[58\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[59\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[60\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[61\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_longint\[63\] (T0 10) (T1 990) (TX 0) (TC 1))
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(fst_parameter\[0\] (T0 0) (T1 1000) (TX 0) (TC 1))
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(fst_parameter\[1\] (T0 0) (T1 1000) (TX 0) (TC 1))
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(fst_parameter\[3\] (T0 0) (T1 1000) (TX 0) (TC 1))
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(fst_parameter\[4\] (T0 0) (T1 1000) (TX 0) (TC 1))
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(fst_parameter\[5\] (T0 0) (T1 1000) (TX 0) (TC 1))
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(fst_parameter\[6\] (T0 0) (T1 1000) (TX 0) (TC 1))
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(fst_lparam\[3\] (T0 0) (T1 1000) (TX 0) (TC 1))
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(fst_lparam\[6\] (T0 0) (T1 1000) (TX 0) (TC 1))
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(fst_lparam\[7\] (T0 0) (T1 1000) (TX 0) (TC 1))
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(fst_lparam\[8\] (T0 0) (T1 1000) (TX 0) (TC 1))
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(fst_supply1 (T0 0) (T1 1000) (TX 0) (TC 1))
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(clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199))
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(rstn (T0 110) (T1 890) (TZ 0) (TX 0) (TB 0) (TC 1))
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(state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46))
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(state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
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(state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
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(state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44))
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(state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
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(state_w\[0\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
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(state_w\[1\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
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(state_w\[2\] (T0 430) (T1 570) (TZ 0) (TX 0) (TB 0) (TC 46))
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(state_w\[3\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 47))
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(state_w\[4\] (T0 420) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 48))
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(state_array[0]\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46))
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(state_array[0]\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
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(state_array[0]\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
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(state_array[0]\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44))
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(state_array[0]\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
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(state_array[1]\[0\] (T0 420) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 47))
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(state_array[1]\[1\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
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(state_array[1]\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
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(state_array[1]\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
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(state_array[1]\[4\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
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(state_array[2]\[0\] (T0 420) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 48))
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(state_array[2]\[1\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
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(state_array[2]\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
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(state_array[2]\[3\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
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(state_array[2]\[4\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 47))
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)
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(INSTANCE test
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(NET
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(clk (T0 505) (T1 495) (TX 0) (TC 199))
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(rstn (T0 110) (T1 890) (TX 0) (TC 1))
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(state\[0\] (T0 410) (T1 590) (TX 0) (TC 46))
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(state\[1\] (T0 540) (T1 460) (TX 0) (TC 45))
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(state\[2\] (T0 530) (T1 470) (TX 0) (TC 46))
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(state\[3\] (T0 540) (T1 460) (TX 0) (TC 44))
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(state\[4\] (T0 540) (T1 460) (TX 0) (TC 45))
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(state_w\[0\] (T0 530) (T1 470) (TX 0) (TC 46))
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(state_w\[1\] (T0 530) (T1 470) (TX 0) (TC 46))
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(state_w\[2\] (T0 430) (T1 570) (TX 0) (TC 46))
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(state_w\[3\] (T0 530) (T1 470) (TX 0) (TC 47))
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(state_w\[4\] (T0 420) (T1 580) (TX 0) (TC 48))
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(state_array[0]\[0\] (T0 410) (T1 590) (TX 0) (TC 46))
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(state_array[0]\[1\] (T0 540) (T1 460) (TX 0) (TC 45))
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(state_array[0]\[2\] (T0 530) (T1 470) (TX 0) (TC 46))
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(state_array[0]\[3\] (T0 540) (T1 460) (TX 0) (TC 44))
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(state_array[0]\[4\] (T0 540) (T1 460) (TX 0) (TC 45))
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(state_array[1]\[0\] (T0 420) (T1 580) (TX 0) (TC 47))
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(state_array[1]\[1\] (T0 530) (T1 470) (TX 0) (TC 46))
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(state_array[1]\[2\] (T0 530) (T1 470) (TX 0) (TC 46))
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(state_array[1]\[3\] (T0 540) (T1 460) (TX 0) (TC 45))
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(state_array[1]\[4\] (T0 530) (T1 470) (TX 0) (TC 46))
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(state_array[2]\[0\] (T0 420) (T1 580) (TX 0) (TC 48))
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(state_array[2]\[1\] (T0 530) (T1 470) (TX 0) (TC 46))
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(state_array[2]\[2\] (T0 530) (T1 470) (TX 0) (TC 46))
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(state_array[2]\[3\] (T0 530) (T1 470) (TX 0) (TC 46))
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(state_array[2]\[4\] (T0 530) (T1 470) (TX 0) (TC 47))
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)
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(INSTANCE unnamedblk1
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(NET
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(i\[0\] (T0 10) (T1 990) (TX 0) (TC 1))
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(i\[1\] (T0 10) (T1 990) (TX 0) (TC 1))
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)
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)
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(INSTANCE unnamedblk2
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(NET
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(i\[1\] (T0 120) (T1 880) (TX 0) (TC 1))
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)
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)
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(INSTANCE unnamedblk1
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(NET
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(i\[0\] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
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(i\[1\] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
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)
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)
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(INSTANCE unnamedblk2
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(NET
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(i\[1\] (T0 120) (T1 880) (TZ 0) (TX 0) (TB 0) (TC 1))
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)
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)
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)
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)
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)
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)
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)
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@ -11,7 +11,7 @@ import vltest_bootstrap
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test.scenarios('vlt_all')
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test.top_filename = "t/t_trace_saif.v"
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test.top_filename = "t/t_trace_fst.v"
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test.golden_filename = "t/t_trace_saif.out"
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test.compile(v_flags2=["--trace-saif"])
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@ -1,96 +0,0 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Outputs
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state,
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// Inputs
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clk
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);
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input clk;
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int cyc;
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reg rstn;
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output [4:0] state;
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integer fst_integer;
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bit fst_bit;
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logic fst_logic;
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int fst_int;
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shortint fst_shortint;
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reg [128:0] fst_longint;
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byte fst_byte;
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parameter fst_parameter = 123;
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localparam fst_lparam = 456;
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supply0 fst_supply0;
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supply1 fst_supply1;
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wire fst_wire;
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Test test (/*AUTOINST*/
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// Outputs
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.state (state[4:0]),
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// Inputs
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.clk (clk),
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.rstn (rstn));
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// Test loop
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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fst_longint [ 0 +: 128 ] <= 128'hbeefbeefbeefbeef;
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if (cyc==0) begin
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// Setup
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rstn <= ~'1;
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end
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else if (cyc<10) begin
|
||||
rstn <= ~'1;
|
||||
end
|
||||
else if (cyc<90) begin
|
||||
rstn <= ~'0;
|
||||
end
|
||||
else if (cyc==99) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module Test (
|
||||
input clk,
|
||||
input rstn,
|
||||
output logic [4:0] state
|
||||
);
|
||||
|
||||
logic [4:0] state_w;
|
||||
logic [4:0] state_array [3];
|
||||
assign state = state_array[0];
|
||||
|
||||
always_comb begin
|
||||
state_w[4] = state_array[2][0];
|
||||
state_w[3] = state_array[2][4];
|
||||
state_w[2] = state_array[2][3] ^ state_array[2][0];
|
||||
state_w[1] = state_array[2][2];
|
||||
state_w[0] = state_array[2][1];
|
||||
end
|
||||
|
||||
always_ff @(posedge clk or negedge rstn) begin
|
||||
if (!rstn) begin
|
||||
for (int i = 0; i < 3; i++)
|
||||
state_array[i] <= 'b1;
|
||||
end
|
||||
else begin
|
||||
for (int i = 0; i < 2; i++)
|
||||
state_array[i] <= state_array[i+1];
|
||||
state_array[2] <= state_w;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue