Fix genvar error with `-O0` (#6165).

Changes

@@ -15,6 +15,7 @@ Verilator 5.039 devel
 
 * Support disable dotted references (#6154). [Ryszard Rozak, Antmicro Ltd.]
 * Fix class extends dotted error (#6162). [Igor Zaworski]
+* Fix genvar error with `-O0` (#6165). [Max Wipfli]
 
 
 Verilator 5.038 2025-07-08

src/V3EmitCBase.cpp

@@ -181,7 +181,7 @@ void EmitCBaseVisitorConst::emitCFuncDecl(const AstCFunc* funcp, const AstNodeMo
 
 void EmitCBaseVisitorConst::emitVarDecl(const AstVar* nodep, bool asRef) {
     const AstBasicDType* const basicp = nodep->basicp();
-    bool refNeedParens = VN_IS(nodep->dtypeSkipRefp(), UnpackArrayDType);
+    const bool refNeedParens = VN_IS(nodep->dtypeSkipRefp(), UnpackArrayDType);
 
     const auto emitDeclArrayBrackets = [this](const AstVar* nodep) -> void {
         // This isn't very robust and may need cleanup for other data types

src/V3EmitCHeaders.cpp

@@ -109,7 +109,8 @@ class EmitCHeader final : public EmitCConstInit {
         // Emit variables in consecutive anon and non-anon batches
         for (const AstNode* nodep = modp->stmtsp(); nodep; nodep = nodep->nextp()) {
             if (const AstVar* const varp = VN_CAST(nodep, Var)) {
-                if (varp->isIO() || varp->isSignal() || varp->isClassMember() || varp->isTemp()) {
+                if (varp->isIO() || varp->isSignal() || varp->isClassMember() || varp->isTemp()
+                    || varp->isGenVar()) {
                     const bool anon = isAnonOk(varp);
                     if (anon != lastAnon) emitCurrentList();
                     lastAnon = anon;

test_regress/t/t_opt_0.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=['-O0'])
+
+test.passes()

test_regress/t/t_opt_0.v

@@ -0,0 +1,14 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+  for (genvar k = 0; k < 1; k++) begin : gen_empty
+    // empty
+  end
+  initial for (int i = 0; i < 1; i++) begin : gen_i
+    // empty
+  end
+endmodule