Fix segfault on type casts (#6574).

Changes

@@ -114,6 +114,7 @@ Verilator 5.041 devel
 * Fix hierarchical with parameterized instances under hier block (#6572). [Geza Lore]
 * Fix references to interfaces containing generate blocks (#6579). [Ryszard Rozak, Antmicro Ltd.]
 * Fix missing net type mappings in FST traces (#6582) (#6583). [Matt Stroud]
+* Fix segfault on type casts (#6574). [David Moberg]
 
 
 Verilator 5.040 2025-08-30

src/V3AstNodeDType.h

@@ -1214,6 +1214,7 @@ public:
         return subDTypep() ? subDTypep()->basicp() : nullptr;
     }
     AstNodeDType* subDTypep() const override VL_MT_STABLE;
+    AstNodeDType* getChildDTypep() const override { return VN_CAST(typeofp(), NodeDType); }
     int widthAlignBytes() const override { return dtypeSkipRefp()->widthAlignBytes(); }
     int widthTotalBytes() const override { return dtypeSkipRefp()->widthTotalBytes(); }
     void name(const string& flag) override { m_name = flag; }

test_regress/t/t_stream_type.py

@@ -0,0 +1,19 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+# Doesn't currently compile due to issue #6574
+test.compile(verilator_make_gmake=False)
+
+# test.execute()
+
+test.passes()

test_regress/t/t_stream_type.v

@@ -0,0 +1,33 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+// verilog_format: off
+`define stop $stop
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
+
+module t;
+  initial begin
+    bit b;
+    automatic reg [2:0] foo0 [1:0] = '{0, 0};
+    automatic reg [2:0] foo2 [1:0] = '{0, 2};
+    automatic reg [2:0] foo4 [1:0] = '{1, 0};
+
+    b = |type(logic [$bits(foo0)-1:0])'({>>{foo0}});
+    $display("foo0 %p -> %b", foo0, b);
+    `checkh(b, 1'b0);
+
+    b = |type(logic [$bits(foo2)-1:0])'({>>{foo2}});
+    $display("foo0 %p -> %b", foo2, b);
+    `checkh(b, 1'b1);
+
+    b = |type(logic [$bits(foo4)-1:0])'({>>{foo4}});
+    $display("foo0 %p -> %b", foo4, b);
+    `checkh(b, 1'b1);
+
+    $finish;
+  end
+endmodule