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Added verilator_coverage test for covergroups 

Signed-off-by: Matthew Ballance <matt.ballance@gmail.com>
This commit is contained in:
Matthew Ballance 2026-03-26 16:20:19 +00:00
parent bf035d17f3
commit 9f4ba736ef
3 changed files with 67 additions and 0 deletions
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31
test_regress/t/t_vlcov_covergroup.out Normal file
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COVERGROUP COVERAGE REPORT
==========================
TOTAL: 3/6 bins covered (50.00%)
(1 ignored, 1 illegal)
------------------------------------------------------------------------------
Covergroup Type: mycg [t/t_vlcov_covergroup_data.dat:10]
Type Coverage: 3/6 bins (50.00%)
Coverpoint: cp_b
Coverage: 1/1 bins (100.00%)
Bins:
IGNORE b_skip 1 hits
ILLEGAL b_bad 0 hits
COVERED b0 2 hits
Cross: cp_a_x_cp_b
Coverage: 1/3 bins (33.33%)
Bins:
ZERO high_x_b0 0 hits
COVERED low_x_b0 2 hits
ZERO low_x_b_skip 0 hits
Coverpoint: cp_a
Coverage: 1/2 bins (50.00%)
Bins:
COVERED low 3 hits
ZERO high 0 hits
------------------------------------------------------------------------------

26
test_regress/t/t_vlcov_covergroup.py Normal file
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#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('dist')
test.run(cmd=[
os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage",
"--covergroup",
test.t_dir + "/t_vlcov_covergroup_data.dat",
],
logfile=test.obj_dir + "/covergroup.log",
tee=False,
verilator_run=True)
test.files_identical(test.obj_dir + "/covergroup.log", test.golden_filename)
test.passes()

10
test_regress/t/t_vlcov_covergroup_data.dat Normal file
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# SystemC::Coverage-3
C 'tlinepagev_line/tft/t_vlcov_covergroup_data.datl10htop.t' 5
C 'tcovergrouppagev_covergroup/mycgft/t_vlcov_covergroup_data.datl5n4binlowhmycg.cp_a.low' 3
C 'tcovergrouppagev_covergroup/mycgft/t_vlcov_covergroup_data.datl6n4binhighhmycg.cp_a.high' 0
C 'tcovergrouppagev_covergroup/mycgft/t_vlcov_covergroup_data.datl9n4binb0hmycg.cp_b.b0' 2
C 'tcovergrouppagev_covergroup/mycgft/t_vlcov_covergroup_data.datl10n4binb_skipbin_typeignorehmycg.cp_b.b_skip' 1
C 'tcovergrouppagev_covergroup/mycgft/t_vlcov_covergroup_data.datl11n4binb_badbin_typeillegalhmycg.cp_b.b_bad' 0
C 'tcovergrouppagev_covergroup/mycgft/t_vlcov_covergroup_data.datl13n7binlow_x_b0cross1hmycg.cp_a_x_cp_b.low_x_b0' 2
C 'tcovergrouppagev_covergroup/mycgft/t_vlcov_covergroup_data.datl13n7binhigh_x_b0cross1hmycg.cp_a_x_cp_b.high_x_b0' 0
C 'tcovergrouppagev_covergroup/mycgft/t_vlcov_covergroup_data.datl13n7binlow_x_b_skipcross1hmycg.cp_a_x_cp_b.low_x_b_skip' 0