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Internals: Do not optimize variables with RW refs in Dfg
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+15
-1
@@ -246,7 +246,8 @@ class DataflowOptimize final {
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// - bit1: Written via AstVarXRef (hierarchical reference)
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// - bit2: Read by logic in same module/netlist not represented in DFG
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// - bit3: Written by logic in same module/netlist not represented in DFG
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// - bit31-4: Reference count, how many DfgVertexVar represent this variable
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// - bit4: Has READWRITE references
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// - bit31-5: Reference count, how many DfgVertexVar represent this variable
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//
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// AstNode::user2/user3/user4 can be used by various DFG algorithms
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const VNUser1InUse m_user1InUse;
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@@ -285,6 +286,12 @@ class DataflowOptimize final {
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senItemp->foreach([](const AstVarRef* refp) {
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DfgVertexVar::setHasExtRdRefs(refp->varScopep());
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});
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return;
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}
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// Check direct references
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if (const AstVarRef* const refp = VN_CAST(nodep, VarRef)) {
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if (refp->access().isRW()) DfgVertexVar::setHasRWRefs(refp->varScopep());
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return;
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}
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} else {
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if (AstVar* const varp = VN_CAST(nodep, Var)) {
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@@ -296,13 +303,20 @@ class DataflowOptimize final {
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if (hasExtWr) DfgVertexVar::setHasExtWrRefs(varp);
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return;
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}
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// Check direct references
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if (const AstVarRef* const refp = VN_CAST(nodep, VarRef)) {
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if (refp->access().isRW()) DfgVertexVar::setHasRWRefs(refp->varp());
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return;
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}
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}
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// Check hierarchical references
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if (const AstVarXRef* const xrefp = VN_CAST(nodep, VarXRef)) {
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AstVar* const tgtp = xrefp->varp();
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if (!tgtp) return;
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if (xrefp->access().isReadOrRW()) DfgVertexVar::setHasExtRdRefs(tgtp);
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if (xrefp->access().isWriteOrRW()) DfgVertexVar::setHasExtWrRefs(tgtp);
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if (xrefp->access().isRW()) DfgVertexVar::setHasRWRefs(tgtp);
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return;
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}
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// Check cell ports
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