Fix SystemC 2.2 deprecated warnings about sensitive() and sc_start().

Changes

@@ -11,6 +11,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Minor performance improvements of Verilator compiler runtime.
 
+**** Fix SystemC 2.2 deprecated warnings about sensitive() and sc_start().
+
 **** Fix arrayed variables under function not compiling, bug44. [Ralf Karge]
 
 **** Fix --output-split-cfuncs to also split trace code. [Niranjan Prabhu]

bin/verilator

@@ -720,7 +720,7 @@ This is an example similar to the above, but using SystemPerl.
           Vour* top;
           top = new Vour("top");   // SP_CELL (top, Vour);
           top->clk(clk);           // SP_PIN  (top, clk, clk);
-          while (!Verilated::gotFinish()) { sc_start(1); }
+          while (!Verilated::gotFinish()) { sc_start(1, SC_NS); }
           exit(0);
       }
     EOF

src/V3EmitC.cpp

@@ -1351,7 +1351,7 @@ void EmitCImp::emitSensitives() {
 	for (AstNode* nodep=m_modp->stmtsp(); nodep; nodep = nodep->nextp()) {
 	    if (AstVar* varp = nodep->castVar()) {
 		if (varp->isInput() && (varp->isScSensitive() || varp->isUsedClock())) {
-		    puts("sensitive("+varp->name()+");\n");
+		    puts("sensitive << "+varp->name()+";\n");
 		}
 	    }
 	}

src/V3LanguageWords.h

@@ -116,6 +116,7 @@ class V3LanguageWords {
 	addKwd("sc_inout",		"SystemC common word");
 	addKwd("sc_out",		"SystemC common word");
 	addKwd("sc_signal",		"SystemC common word");
+	addKwd("sensitive",		"SystemC common word");
 	addKwd("sensitive_neg",		"SystemC common word");
 	addKwd("sensitive_pos",		"SystemC common word");
     }

test_regress/driver.pl

@@ -678,7 +678,11 @@ sub _make_main {
 	    $action = 1;
 	}
 	if ($self->sc_or_sp) {
+	    print $fh "#if (SYSTEMC_VERSION>=20070314)\n";
+	    print $fh "	sc_start(1,SC_NS);\n";
+	    print $fh "#else\n";
 	    print $fh "	sc_start(1);\n";
+	    print $fh "#endif\n";
 	} else {
 	    print $fh "	main_time+=1;\n";
 	    print $fh "	${set}eval();\n" if $action;

test_sp/sc_main.cpp

@@ -45,9 +45,16 @@ int sc_main(int argc, char* argv[]) {
     //==========
     // Define the Clocks
 
-    cout << ("Defining Clocks\n");
-    sc_clock clk     ("clk",10, 0.5, 3, true);
-    sc_clock fastclk ("fastclk",2, 0.5, 2, true);
+    cout << "Defining Clocks\n";
+#if (SYSTEMC_VERSION>=20070314)
+    sc_clock clk     ("clk",    10,SC_NS, 0.5, 3,SC_NS, true);
+    sc_clock fastclk ("fastclk", 2,SC_NS, 0.5, 2,SC_NS, true);
+#else
+    sc_clock clk     ("clk",    10, 0.5, 3, true);
+    sc_clock fastclk ("fastclk", 2, 0.5, 2, true);
+#endif
+
+    cout << "Defining Interconnect\n";
     sc_signal<bool> reset_l;
     sc_signal<bool> passed;
     sc_signal<uint32_t> in_small;
@@ -98,7 +105,11 @@ int sc_main(int argc, char* argv[]) {
     // SystemC to interconnect everything for testing.
     cout <<("Test initialization...\n");
     reset_l = 1;
+#if (SYSTEMC_VERSION>=20070314)
+    sc_start(1,SC_NS);
+#else
     sc_start(1);
+#endif
 
     //==========
     //  Waves
@@ -127,7 +138,11 @@ int sc_main(int argc, char* argv[]) {
 	} else if (VL_TIME_Q() > 1) {
 	    reset_l = 0;	// Assert reset
 	}
+#if (SYSTEMC_VERSION>=20070314)
+	sc_start(1,SC_NS);
+#else
 	sc_start(1);
+#endif
     }
 
     top->final();

test_verilated/vgen.pl

@@ -627,7 +627,7 @@ sub write_output_sc {
     foreach my $block (@Blocks) {
 	print $fh "SP_CTOR_IMP($block->{name}) {\n";
 	print $fh "  SC_METHOD(clkPosedge);\n";
-	print $fh "  sensitive_pos(clk);\n";
+	print $fh "  sensitive << clk.pos();\n";
 	print $fh "}\n\n";
 
 	print $fh "void $block->{name}::clkPosedge() {\n";