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refine test format

This commit is contained in:
Yilou Wang 2026-06-16 15:35:53 +02:00
parent 7bd6c2080f
commit 9cf2fc6568
1 changed files with 4 additions and 7 deletions
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11
test_regress/t/t_cover_property.v
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@ -4,13 +4,10 @@
// SPDX-FileCopyrightText: 2026 PlanV GmbH // SPDX-FileCopyrightText: 2026 PlanV GmbH
// SPDX-License-Identifier: CC0-1.0 // SPDX-License-Identifier: CC0-1.0
`define checkd(gotv, expv) \ // verilog_format: off
do \ `define stop $stop
if ((gotv) !== (expv)) begin \ `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
$write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__, `__LINE__, (gotv), (expv)); \ // verilog_format: on
$stop; \
end \
while (0);
module t ( module t (
input clk input clk