parent
15f8ebc562
commit
9cc218db3e
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@ -334,17 +334,20 @@ class AstToDfgVisitor final : public VNVisitor {
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const uint32_t bEnd = b.m_lsb + bWidth;
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const uint32_t bEnd = b.m_lsb + bWidth;
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const uint32_t overlapEnd = std::min(aEnd, bEnd) - 1;
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const uint32_t overlapEnd = std::min(aEnd, bEnd) - 1;
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varp->varp()->v3warn( //
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if (a.m_fileline->operatorCompare(*b.m_fileline) != 0) {
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MULTIDRIVEN,
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varp->varp()->v3warn( //
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"Bits [" //
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MULTIDRIVEN,
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<< overlapEnd << ":" << b.m_lsb << "] of signal "
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"Bits [" //
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<< varp->varp()->prettyNameQ()
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<< overlapEnd << ":" << b.m_lsb << "] of signal "
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<< " have multiple combinational drivers\n"
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<< varp->varp()->prettyNameQ()
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<< a.m_fileline->warnOther() << "... Location of first driver\n"
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<< " have multiple combinational drivers\n"
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<< a.m_fileline->warnContextPrimary() << '\n'
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<< a.m_fileline->warnOther() << "... Location of first driver\n"
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<< b.m_fileline->warnOther() << "... Location of other driver\n"
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<< a.m_fileline->warnContextPrimary() << '\n'
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<< b.m_fileline->warnContextSecondary() << varp->varp()->warnOther()
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<< b.m_fileline->warnOther() << "... Location of other driver\n"
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<< "... Only the first driver will be respected");
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<< b.m_fileline->warnContextSecondary()
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<< varp->varp()->warnOther()
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<< "... Only the first driver will be respected");
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}
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// If the first driver completely covers the range of the second driver,
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// If the first driver completely covers the range of the second driver,
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// we can just delete the second driver completely, otherwise adjust the
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// we can just delete the second driver completely, otherwise adjust the
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@ -0,0 +1,21 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2023 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(linter => 1);
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top_filename("t/t_incorrect_multi_driven.v");
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lint(
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fails => 0
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);
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ok(1);
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1;
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@ -0,0 +1,56 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2023 by Adrien Le Masle.
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// SPDX-License-Identifier: CC0-1.0
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interface test_if #(parameter int AA = 2, BB=5);
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logic [AA-1 : 0] a;
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logic [BB-1 : 0] b;
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logic c;
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logic d;
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modport slave (input a,
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input b,
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input c,
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input d);
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modport master (output a,
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output b,
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output c,
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output d);
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endinterface : test_if
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module test
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(input logic [28:0] a,
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output logic [28:0] b);
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always_comb begin
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b = a;
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end
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endmodule
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module multi_driven
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(
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input logic [20-1 : 0] data_in,
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output logic [20-1 : 0] data_out,
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test_if.slave test_if_in,
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test_if.master test_if_out
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);
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test test_inst
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(
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.a({data_in,
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test_if_in.a,
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test_if_in.b,
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test_if_in.c,
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test_if_in.d}),
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.b({data_out,
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test_if_out.a,
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test_if_out.b,
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test_if_out.c,
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test_if_out.d}));
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endmodule;
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